30 #define PADS_SCHMITT_EN_REG(pin)	(PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))  argument
31 #define PADS_SCHMITT_EN_BIT(pin)	BIT((pin) % 32)  argument
34 #define PADS_PU_PD_REG(pin)		(PADS_PU_PD0 + 0x4 * ((pin) / 16))  argument
35 #define PADS_PU_PD_SHIFT(pin)		(2 * ((pin) % 16))  argument
48 #define PADS_SLEW_RATE_REG(pin)		(PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))  argument
49 #define PADS_SLEW_RATE_BIT(pin)		BIT((pin) % 32)  argument
52 #define PADS_DRIVE_STRENGTH_REG(pin)					\  argument
53 	(PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
54 #define PADS_DRIVE_STRENGTH_SHIFT(pin)	(2 * ((pin) % 16))  argument
90 	unsigned int pin;  member
641 		.pin = PISTACHIO_PIN_##_pin,			\
655 		.pin = PISTACHIO_PIN_MFIO(_pin),		\
669 		.pin = PISTACHIO_PIN_MFIO(_pin),			\
910 	*pins = &pctl->groups[group].pin;  in pistachio_pinctrl_get_group_pins()
993 	range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);  in pistachio_pinmux_enable()
995 		gpio_disable(gc_to_bank(range->gc), pg->pin - range->pin_base);  in pistachio_pinmux_enable()
1007 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,  in pistachio_pinconf_get()  argument
1016 		val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_get()
1017 		arg = !!(val & PADS_SCHMITT_EN_BIT(pin));  in pistachio_pinconf_get()
1020 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1021 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1025 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1026 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1030 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1031 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1035 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1036 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1040 		val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_get()
1041 		arg = !!(val & PADS_SLEW_RATE_BIT(pin));  in pistachio_pinconf_get()
1044 		val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>  in pistachio_pinconf_get()
1045 			PADS_DRIVE_STRENGTH_SHIFT(pin);  in pistachio_pinconf_get()
1072 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,  in pistachio_pinconf_set()  argument
1086 			val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_set()
1088 				val |= PADS_SCHMITT_EN_BIT(pin);  in pistachio_pinconf_set()
1090 				val &= ~PADS_SCHMITT_EN_BIT(pin);  in pistachio_pinconf_set()
1091 			pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_set()
1094 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1095 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1096 			val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1097 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1100 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1101 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1102 			val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1103 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1106 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1107 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1108 			val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1109 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1112 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1113 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1114 			val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1115 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1118 			val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_set()
1120 				val |= PADS_SLEW_RATE_BIT(pin);  in pistachio_pinconf_set()
1122 				val &= ~PADS_SLEW_RATE_BIT(pin);  in pistachio_pinconf_set()
1123 			pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_set()
1126 			val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));  in pistachio_pinconf_set()
1128 				 PADS_DRIVE_STRENGTH_SHIFT(pin));  in pistachio_pinconf_set()
1148 			val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);  in pistachio_pinconf_set()
1149 			pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));  in pistachio_pinconf_set()
1309 	unsigned int pin;  in pistachio_gpio_irq_handler()  local
1314 	for_each_set_bit(pin, &pending, 16)  in pistachio_gpio_irq_handler()
1315 		generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));  in pistachio_gpio_irq_handler()