Lines Matching refs:BIT
57 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_direction_input()
59 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_direction_input()
62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
80 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
99 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
111 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
161 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
166 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
229 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
232 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) in amd_gpio_dbg_show()
233 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) in amd_gpio_dbg_show()
235 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) in amd_gpio_dbg_show()
236 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) in amd_gpio_dbg_show()
238 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) in amd_gpio_dbg_show()
239 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) in amd_gpio_dbg_show()
244 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
256 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
263 if (pin_reg & BIT(WAKE_CNTRL_OFF)) in amd_gpio_dbg_show()
268 if (pin_reg & BIT(WAKE_CNTRL_OFF)) in amd_gpio_dbg_show()
273 if (pin_reg & BIT(WAKE_CNTRL_OFF)) in amd_gpio_dbg_show()
278 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
280 if (pin_reg & BIT(PULL_UP_SEL_OFF)) in amd_gpio_dbg_show()
289 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) in amd_gpio_dbg_show()
294 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
297 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
305 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
340 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_irq_enable()
341 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_irq_enable()
343 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
344 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
358 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
359 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
373 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
387 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
419 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
427 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
435 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
525 if (reg64 & BIT(off)) { in amd_gpio_irq_handler()
529 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || in amd_gpio_irq_handler()
530 (pin_reg & BIT(WAKE_STS_OFF))) { in amd_gpio_irq_handler()
611 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
615 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); in amd_pinconf_get()
657 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
658 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
662 pin_reg &= ~BIT(PULL_UP_SEL_OFF); in amd_pinconf_set()
663 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; in amd_pinconf_set()
664 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
665 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()