Lines Matching refs:ctx
605 static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, in cmu_wr() argument
608 void __iomem *sds_base = ctx->sds_base; in cmu_wr()
622 static void cmu_rd(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, in cmu_rd() argument
625 void __iomem *sds_base = ctx->sds_base; in cmu_rd()
636 static void cmu_toggle1to0(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, in cmu_toggle1to0() argument
641 cmu_rd(ctx, cmu_type, reg, &val); in cmu_toggle1to0()
643 cmu_wr(ctx, cmu_type, reg, val); in cmu_toggle1to0()
644 cmu_rd(ctx, cmu_type, reg, &val); in cmu_toggle1to0()
646 cmu_wr(ctx, cmu_type, reg, val); in cmu_toggle1to0()
649 static void cmu_clrbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, in cmu_clrbits() argument
654 cmu_rd(ctx, cmu_type, reg, &val); in cmu_clrbits()
656 cmu_wr(ctx, cmu_type, reg, val); in cmu_clrbits()
659 static void cmu_setbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, in cmu_setbits() argument
664 cmu_rd(ctx, cmu_type, reg, &val); in cmu_setbits()
666 cmu_wr(ctx, cmu_type, reg, val); in cmu_setbits()
669 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
671 void __iomem *sds_base = ctx->sds_base; in serdes_wr()
684 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
686 void __iomem *sds_base = ctx->sds_base; in serdes_rd()
695 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
700 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
702 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
705 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
710 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
712 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
715 static void xgene_phy_cfg_cmu_clk_type(struct xgene_phy_ctx *ctx, in xgene_phy_cfg_cmu_clk_type() argument
722 cmu_rd(ctx, cmu_type, CMU_REG12, &val); in xgene_phy_cfg_cmu_clk_type()
724 cmu_wr(ctx, cmu_type, CMU_REG12, val); in xgene_phy_cfg_cmu_clk_type()
726 cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222); in xgene_phy_cfg_cmu_clk_type()
727 cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225); in xgene_phy_cfg_cmu_clk_type()
732 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_cfg_cmu_clk_type()
734 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_cfg_cmu_clk_type()
736 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
738 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
739 dev_dbg(ctx->dev, "Set external reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
742 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_cfg_cmu_clk_type()
744 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_cfg_cmu_clk_type()
746 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
748 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
749 dev_dbg(ctx->dev, "Set internal reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
757 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
759 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
761 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cfg_cmu_clk_type()
763 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cfg_cmu_clk_type()
764 dev_dbg(ctx->dev, in xgene_phy_cfg_cmu_clk_type()
769 static void xgene_phy_sata_cfg_cmu_core(struct xgene_phy_ctx *ctx, in xgene_phy_sata_cfg_cmu_core() argument
778 cmu_rd(ctx, cmu_type, CMU_REG34, &val); in xgene_phy_sata_cfg_cmu_core()
783 cmu_wr(ctx, cmu_type, CMU_REG34, val); in xgene_phy_sata_cfg_cmu_core()
787 cmu_rd(ctx, cmu_type, CMU_REG0, &val); in xgene_phy_sata_cfg_cmu_core()
792 cmu_wr(ctx, cmu_type, CMU_REG0, val); in xgene_phy_sata_cfg_cmu_core()
795 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_sata_cfg_cmu_core()
805 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_sata_cfg_cmu_core()
808 cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_sata_cfg_cmu_core()
811 cmu_rd(ctx, cmu_type, CMU_REG2, &val); in xgene_phy_sata_cfg_cmu_core()
829 cmu_wr(ctx, cmu_type, CMU_REG2, val); in xgene_phy_sata_cfg_cmu_core()
832 cmu_rd(ctx, cmu_type, CMU_REG3, &val); in xgene_phy_sata_cfg_cmu_core()
844 cmu_wr(ctx, cmu_type, CMU_REG3, val); in xgene_phy_sata_cfg_cmu_core()
847 cmu_rd(ctx, cmu_type, CMU_REG26, &val); in xgene_phy_sata_cfg_cmu_core()
849 cmu_wr(ctx, cmu_type, CMU_REG26, val); in xgene_phy_sata_cfg_cmu_core()
852 cmu_rd(ctx, cmu_type, CMU_REG5, &val); in xgene_phy_sata_cfg_cmu_core()
859 cmu_wr(ctx, cmu_type, CMU_REG5, val); in xgene_phy_sata_cfg_cmu_core()
862 cmu_rd(ctx, cmu_type, CMU_REG6, &val); in xgene_phy_sata_cfg_cmu_core()
865 cmu_wr(ctx, cmu_type, CMU_REG6, val); in xgene_phy_sata_cfg_cmu_core()
869 cmu_rd(ctx, cmu_type, CMU_REG9, &val); in xgene_phy_sata_cfg_cmu_core()
879 cmu_wr(ctx, cmu_type, CMU_REG9, val); in xgene_phy_sata_cfg_cmu_core()
882 cmu_rd(ctx, cmu_type, CMU_REG10, &val); in xgene_phy_sata_cfg_cmu_core()
884 cmu_wr(ctx, cmu_type, CMU_REG10, val); in xgene_phy_sata_cfg_cmu_core()
888 cmu_rd(ctx, cmu_type, CMU_REG16, &val); in xgene_phy_sata_cfg_cmu_core()
895 cmu_wr(ctx, cmu_type, CMU_REG16, val); in xgene_phy_sata_cfg_cmu_core()
898 cmu_rd(ctx, cmu_type, CMU_REG30, &val); in xgene_phy_sata_cfg_cmu_core()
901 cmu_wr(ctx, cmu_type, CMU_REG30, val); in xgene_phy_sata_cfg_cmu_core()
904 cmu_wr(ctx, cmu_type, CMU_REG31, 0xF); in xgene_phy_sata_cfg_cmu_core()
906 cmu_rd(ctx, cmu_type, CMU_REG32, &val); in xgene_phy_sata_cfg_cmu_core()
912 cmu_wr(ctx, cmu_type, CMU_REG32, val); in xgene_phy_sata_cfg_cmu_core()
916 cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27); in xgene_phy_sata_cfg_cmu_core()
918 cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c); in xgene_phy_sata_cfg_cmu_core()
921 cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F); in xgene_phy_sata_cfg_cmu_core()
924 static void xgene_phy_ssc_enable(struct xgene_phy_ctx *ctx, in xgene_phy_ssc_enable() argument
930 cmu_rd(ctx, cmu_type, CMU_REG35, &val); in xgene_phy_ssc_enable()
932 cmu_wr(ctx, cmu_type, CMU_REG35, val); in xgene_phy_ssc_enable()
935 cmu_rd(ctx, cmu_type, CMU_REG36, &val); in xgene_phy_ssc_enable()
939 cmu_wr(ctx, cmu_type, CMU_REG36, val); in xgene_phy_ssc_enable()
942 cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_ssc_enable()
943 cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_ssc_enable()
946 cmu_toggle1to0(ctx, cmu_type, CMU_REG32, in xgene_phy_ssc_enable()
950 static void xgene_phy_sata_cfg_lanes(struct xgene_phy_ctx *ctx) in xgene_phy_sata_cfg_lanes() argument
958 serdes_wr(ctx, lane, RXTX_REG147, 0x6); in xgene_phy_sata_cfg_lanes()
961 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
965 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
968 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
971 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
972 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
973 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
977 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
981 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
984 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
986 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
989 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
992 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
996 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
998 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
999 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
1002 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1004 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
1005 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1006 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
1009 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
1011 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1012 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1017 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1020 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1023 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1026 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1032 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1035 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1037 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1040 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1044 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1047 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1050 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1052 serdes_wr(ctx, lane, RXTX_REG28, 0x0); in xgene_phy_sata_cfg_lanes()
1055 serdes_wr(ctx, lane, RXTX_REG31, 0x0); in xgene_phy_sata_cfg_lanes()
1058 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1062 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1064 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1066 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1071 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1075 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1081 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1085 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1091 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1095 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1098 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1100 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1102 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); in xgene_phy_sata_cfg_lanes()
1104 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1106 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1107 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1109 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1110 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1112 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1114 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1116 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1118 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1120 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1122 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1132 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1140 serdes_wr(ctx, lane, reg, 0xFFFF); in xgene_phy_sata_cfg_lanes()
1145 static int xgene_phy_cal_rdy_chk(struct xgene_phy_ctx *ctx, in xgene_phy_cal_rdy_chk() argument
1149 void __iomem *csr_serdes = ctx->sds_base; in xgene_phy_cal_rdy_chk()
1158 cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); in xgene_phy_cal_rdy_chk()
1165 cmu_rd(ctx, cmu_type, CMU_REG1, &val); in xgene_phy_cal_rdy_chk()
1167 cmu_wr(ctx, cmu_type, CMU_REG1, val); in xgene_phy_cal_rdy_chk()
1174 cmu_toggle1to0(ctx, cmu_type, CMU_REG32, in xgene_phy_cal_rdy_chk()
1191 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1194 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1195 cmu_toggle1to0(ctx, cmu_type, CMU_REG17, in xgene_phy_cal_rdy_chk()
1202 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1205 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1206 cmu_toggle1to0(ctx, cmu_type, CMU_REG16, in xgene_phy_cal_rdy_chk()
1209 cmu_rd(ctx, cmu_type, CMU_REG17, &val); in xgene_phy_cal_rdy_chk()
1212 cmu_wr(ctx, cmu_type, CMU_REG17, val); in xgene_phy_cal_rdy_chk()
1213 cmu_toggle1to0(ctx, cmu_type, CMU_REG16, in xgene_phy_cal_rdy_chk()
1220 cmu_rd(ctx, cmu_type, CMU_REG7, &val); in xgene_phy_cal_rdy_chk()
1230 cmu_rd(ctx, cmu_type, CMU_REG7, &val); in xgene_phy_cal_rdy_chk()
1231 dev_dbg(ctx->dev, "PLL calibration %s\n", in xgene_phy_cal_rdy_chk()
1234 dev_err(ctx->dev, in xgene_phy_cal_rdy_chk()
1238 dev_dbg(ctx->dev, "PLL calibration successful\n"); in xgene_phy_cal_rdy_chk()
1240 cmu_rd(ctx, cmu_type, CMU_REG15, &val); in xgene_phy_cal_rdy_chk()
1241 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1245 static void xgene_phy_pdwn_force_vco(struct xgene_phy_ctx *ctx, in xgene_phy_pdwn_force_vco() argument
1251 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); in xgene_phy_pdwn_force_vco()
1253 cmu_rd(ctx, cmu_type, CMU_REG16, &val); in xgene_phy_pdwn_force_vco()
1255 cmu_wr(ctx, cmu_type, CMU_REG16, val); in xgene_phy_pdwn_force_vco()
1258 cmu_toggle1to0(ctx, cmu_type, CMU_REG0, CMU_REG0_PDOWN_MASK); in xgene_phy_pdwn_force_vco()
1259 cmu_toggle1to0(ctx, cmu_type, CMU_REG32, in xgene_phy_pdwn_force_vco()
1263 static int xgene_phy_hw_init_sata(struct xgene_phy_ctx *ctx, in xgene_phy_hw_init_sata() argument
1266 void __iomem *sds_base = ctx->sds_base; in xgene_phy_hw_init_sata()
1271 dev_dbg(ctx->dev, "Reset PHY\n"); in xgene_phy_hw_init_sata()
1285 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1288 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); in xgene_phy_hw_init_sata()
1294 xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type); in xgene_phy_hw_init_sata()
1297 xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type); in xgene_phy_hw_init_sata()
1301 xgene_phy_ssc_enable(ctx, PHY_CMU); in xgene_phy_hw_init_sata()
1304 xgene_phy_sata_cfg_lanes(ctx); in xgene_phy_hw_init_sata()
1315 if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type)) in xgene_phy_hw_init_sata()
1318 xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); in xgene_phy_hw_init_sata()
1322 dev_err(ctx->dev, "PLL calibration failed\n"); in xgene_phy_hw_init_sata()
1327 static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx, in xgene_phy_hw_initialize() argument
1333 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); in xgene_phy_hw_initialize()
1335 if (ctx->mode == MODE_SATA) { in xgene_phy_hw_initialize()
1336 rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable); in xgene_phy_hw_initialize()
1340 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", in xgene_phy_hw_initialize()
1341 ctx->mode); in xgene_phy_hw_initialize()
1354 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_force_lat_summer_cal() argument
1382 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1389 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1398 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1405 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1409 serdes_wr(ctx, lane, RXTX_REG28, 0x7); in xgene_phy_force_lat_summer_cal()
1410 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_force_lat_summer_cal()
1411 serdes_clrbits(ctx, lane, RXTX_REG4, in xgene_phy_force_lat_summer_cal()
1413 serdes_clrbits(ctx, lane, RXTX_REG7, in xgene_phy_force_lat_summer_cal()
1416 serdes_wr(ctx, lane, serdes_reg[i].reg, in xgene_phy_force_lat_summer_cal()
1420 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_reset_rxd() argument
1423 serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1426 serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1434 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_gen_avg_val() argument
1448 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", in xgene_phy_gen_avg_val()
1452 serdes_setbits(ctx, lane, RXTX_REG12, in xgene_phy_gen_avg_val()
1455 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); in xgene_phy_gen_avg_val()
1457 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); in xgene_phy_gen_avg_val()
1468 xgene_phy_force_lat_summer_cal(ctx, lane); in xgene_phy_gen_avg_val()
1470 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1475 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1480 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1484 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1488 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1504 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); in xgene_phy_gen_avg_val()
1505 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1508 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1511 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1514 dev_err(ctx->dev, in xgene_phy_gen_avg_val()
1518 xgene_phy_reset_rxd(ctx, lane); in xgene_phy_gen_avg_val()
1522 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1527 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1529 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1534 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1536 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1541 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1543 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1548 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1551 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1554 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1556 dev_dbg(ctx->dev, "Average Value:\n"); in xgene_phy_gen_avg_val()
1557 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1562 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1567 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1570 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1572 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1573 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); in xgene_phy_gen_avg_val()
1575 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1577 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); in xgene_phy_gen_avg_val()
1578 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1581 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1583 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()
1585 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); in xgene_phy_gen_avg_val()
1587 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_gen_avg_val()
1592 struct xgene_phy_ctx *ctx = phy_get_drvdata(phy); in xgene_phy_hw_init() local
1596 rc = xgene_phy_hw_initialize(ctx, CLK_EXT_DIFF, SSC_DISABLE); in xgene_phy_hw_init()
1598 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); in xgene_phy_hw_init()
1603 if (!IS_ERR(ctx->clk)) { in xgene_phy_hw_init()
1605 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1606 clk_disable_unprepare(ctx->clk); in xgene_phy_hw_init()
1607 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1612 xgene_phy_gen_avg_val(ctx, i); in xgene_phy_hw_init()
1614 dev_dbg(ctx->dev, "PHY initialized\n"); in xgene_phy_hw_init()
1626 struct xgene_phy_ctx *ctx = dev_get_drvdata(dev); in xgene_phy_xlate() local
1633 ctx->mode = args->args[0]; in xgene_phy_xlate()
1634 return ctx->phy; in xgene_phy_xlate()
1658 struct xgene_phy_ctx *ctx; in xgene_phy_probe() local
1670 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in xgene_phy_probe()
1671 if (!ctx) in xgene_phy_probe()
1674 ctx->dev = &pdev->dev; in xgene_phy_probe()
1677 ctx->sds_base = devm_ioremap_resource(&pdev->dev, res); in xgene_phy_probe()
1678 if (IS_ERR(ctx->sds_base)) in xgene_phy_probe()
1679 return PTR_ERR(ctx->sds_base); in xgene_phy_probe()
1682 ctx->clk = clk_get(&pdev->dev, NULL); in xgene_phy_probe()
1686 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); in xgene_phy_probe()
1688 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); in xgene_phy_probe()
1690 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); in xgene_phy_probe()
1692 ctx->sata_param.txamplitude, 6, default_txamp, 13300); in xgene_phy_probe()
1694 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); in xgene_phy_probe()
1696 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); in xgene_phy_probe()
1698 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); in xgene_phy_probe()
1700 ctx->sata_param.txspeed, 3, default_spd, 1); in xgene_phy_probe()
1702 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ in xgene_phy_probe()
1704 platform_set_drvdata(pdev, ctx); in xgene_phy_probe()
1706 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); in xgene_phy_probe()
1707 if (IS_ERR(ctx->phy)) { in xgene_phy_probe()
1709 return PTR_ERR(ctx->phy); in xgene_phy_probe()
1711 phy_set_drvdata(ctx->phy, ctx); in xgene_phy_probe()
1713 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); in xgene_phy_probe()