605 static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,  in cmu_wr()  function
643 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_toggle1to0()
646 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_toggle1to0()
656 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_clrbits()
666 	cmu_wr(ctx, cmu_type, reg, val);  in cmu_setbits()
724 	cmu_wr(ctx, cmu_type, CMU_REG12, val);  in xgene_phy_cfg_cmu_clk_type()
726 	cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222);  in xgene_phy_cfg_cmu_clk_type()
727 	cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225);  in xgene_phy_cfg_cmu_clk_type()
734 		cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_cfg_cmu_clk_type()
738 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
744 		cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_cfg_cmu_clk_type()
748 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
759 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
763 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cfg_cmu_clk_type()
783 		cmu_wr(ctx, cmu_type, CMU_REG34, val);  in xgene_phy_sata_cfg_cmu_core()
792 	cmu_wr(ctx, cmu_type, CMU_REG0, val);  in xgene_phy_sata_cfg_cmu_core()
805 	cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_sata_cfg_cmu_core()
829 	cmu_wr(ctx, cmu_type, CMU_REG2, val);  in xgene_phy_sata_cfg_cmu_core()
844 	cmu_wr(ctx, cmu_type, CMU_REG3, val);  in xgene_phy_sata_cfg_cmu_core()
849 	cmu_wr(ctx, cmu_type, CMU_REG26, val);  in xgene_phy_sata_cfg_cmu_core()
859 	cmu_wr(ctx, cmu_type, CMU_REG5, val);  in xgene_phy_sata_cfg_cmu_core()
865 	cmu_wr(ctx, cmu_type, CMU_REG6, val);  in xgene_phy_sata_cfg_cmu_core()
879 		cmu_wr(ctx, cmu_type, CMU_REG9, val);  in xgene_phy_sata_cfg_cmu_core()
884 			cmu_wr(ctx, cmu_type, CMU_REG10, val);  in xgene_phy_sata_cfg_cmu_core()
895 	cmu_wr(ctx, cmu_type, CMU_REG16, val);  in xgene_phy_sata_cfg_cmu_core()
901 	cmu_wr(ctx, cmu_type, CMU_REG30, val);  in xgene_phy_sata_cfg_cmu_core()
904 	cmu_wr(ctx, cmu_type, CMU_REG31, 0xF);  in xgene_phy_sata_cfg_cmu_core()
912 	cmu_wr(ctx, cmu_type, CMU_REG32, val);  in xgene_phy_sata_cfg_cmu_core()
916 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27);  in xgene_phy_sata_cfg_cmu_core()
918 		cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c);  in xgene_phy_sata_cfg_cmu_core()
921 	cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F);  in xgene_phy_sata_cfg_cmu_core()
932 	cmu_wr(ctx, cmu_type, CMU_REG35, val);  in xgene_phy_ssc_enable()
939 	cmu_wr(ctx, cmu_type, CMU_REG36, val);  in xgene_phy_ssc_enable()
1167 		cmu_wr(ctx, cmu_type, CMU_REG1, val);  in xgene_phy_cal_rdy_chk()
1194 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1205 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1212 	cmu_wr(ctx, cmu_type, CMU_REG17, val);  in xgene_phy_cal_rdy_chk()
1255 		cmu_wr(ctx, cmu_type, CMU_REG16, val);  in xgene_phy_pdwn_force_vco()