125 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)  in ti_pipe3_get_dpll_params()  argument
128 	struct pipe3_dpll_map *dpll_map = phy->dpll_map;  in ti_pipe3_get_dpll_params()
130 	rate = clk_get_rate(phy->sys_clk);  in ti_pipe3_get_dpll_params()
137 	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);  in ti_pipe3_get_dpll_params()
142 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
143 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
145 static int ti_pipe3_power_off(struct phy *x)  in ti_pipe3_power_off()
147 	struct ti_pipe3 *phy = phy_get_drvdata(x);  in ti_pipe3_power_off()  local
149 	omap_control_phy_power(phy->control_dev, 0);  in ti_pipe3_power_off()
154 static int ti_pipe3_power_on(struct phy *x)  in ti_pipe3_power_on()
156 	struct ti_pipe3 *phy = phy_get_drvdata(x);  in ti_pipe3_power_on()  local
158 	omap_control_phy_power(phy->control_dev, 1);  in ti_pipe3_power_on()
163 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)  in ti_pipe3_dpll_wait_lock()  argument
171 		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in ti_pipe3_dpll_wait_lock()
176 	dev_err(phy->dev, "DPLL failed to lock\n");  in ti_pipe3_dpll_wait_lock()
180 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)  in ti_pipe3_dpll_program()  argument
185 	dpll_params = ti_pipe3_get_dpll_params(phy);  in ti_pipe3_dpll_program()
189 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);  in ti_pipe3_dpll_program()
192 	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);  in ti_pipe3_dpll_program()
194 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in ti_pipe3_dpll_program()
197 	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in ti_pipe3_dpll_program()
199 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);  in ti_pipe3_dpll_program()
202 	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);  in ti_pipe3_dpll_program()
204 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);  in ti_pipe3_dpll_program()
207 	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);  in ti_pipe3_dpll_program()
209 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);  in ti_pipe3_dpll_program()
212 	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);  in ti_pipe3_dpll_program()
214 	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);  in ti_pipe3_dpll_program()
216 	return ti_pipe3_dpll_wait_lock(phy);  in ti_pipe3_dpll_program()
219 static int ti_pipe3_init(struct phy *x)  in ti_pipe3_init()
221 	struct ti_pipe3 *phy = phy_get_drvdata(x);  in ti_pipe3_init()  local
225 	ti_pipe3_enable_clocks(phy);  in ti_pipe3_init()
231 	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {  in ti_pipe3_init()
232 		omap_control_pcie_pcs(phy->control_dev, 0x96);  in ti_pipe3_init()
237 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in ti_pipe3_init()
240 		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in ti_pipe3_init()
241 		ret = ti_pipe3_dpll_wait_lock(phy);  in ti_pipe3_init()
245 	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in ti_pipe3_init()
247 		if (ti_pipe3_dpll_program(phy))  in ti_pipe3_init()
253 static int ti_pipe3_exit(struct phy *x)  in ti_pipe3_exit()
255 	struct ti_pipe3 *phy = phy_get_drvdata(x);  in ti_pipe3_exit()  local
262 	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&  in ti_pipe3_exit()
263 	    !phy->dpll_reset_syscon)  in ti_pipe3_exit()
267 	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {  in ti_pipe3_exit()
269 		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in ti_pipe3_exit()
271 		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in ti_pipe3_exit()
277 			val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in ti_pipe3_exit()
283 			dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",  in ti_pipe3_exit()
290 	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {  in ti_pipe3_exit()
291 		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,  in ti_pipe3_exit()
293 		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,  in ti_pipe3_exit()
297 	ti_pipe3_disable_clocks(phy);  in ti_pipe3_exit()
313 	struct ti_pipe3 *phy;  in ti_pipe3_probe()  local
314 	struct phy *generic_phy;  in ti_pipe3_probe()
323 	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);  in ti_pipe3_probe()
324 	if (!phy)  in ti_pipe3_probe()
327 	phy->dev		= &pdev->dev;  in ti_pipe3_probe()
334 		phy->dpll_map = (struct pipe3_dpll_map *)match->data;  in ti_pipe3_probe()
335 		if (!phy->dpll_map) {  in ti_pipe3_probe()
342 		phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);  in ti_pipe3_probe()
343 		if (IS_ERR(phy->pll_ctrl_base))  in ti_pipe3_probe()
344 			return PTR_ERR(phy->pll_ctrl_base);  in ti_pipe3_probe()
346 		phy->sys_clk = devm_clk_get(phy->dev, "sysclk");  in ti_pipe3_probe()
347 		if (IS_ERR(phy->sys_clk)) {  in ti_pipe3_probe()
353 	phy->refclk = devm_clk_get(phy->dev, "refclk");  in ti_pipe3_probe()
354 	if (IS_ERR(phy->refclk)) {  in ti_pipe3_probe()
360 			return PTR_ERR(phy->refclk);  in ti_pipe3_probe()
364 		phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");  in ti_pipe3_probe()
365 		if (IS_ERR(phy->wkupclk)) {  in ti_pipe3_probe()
367 			return PTR_ERR(phy->wkupclk);  in ti_pipe3_probe()
370 		phy->wkupclk = ERR_PTR(-ENODEV);  in ti_pipe3_probe()
371 		phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,  in ti_pipe3_probe()
373 		if (IS_ERR(phy->dpll_reset_syscon)) {  in ti_pipe3_probe()
376 			phy->dpll_reset_syscon = NULL;  in ti_pipe3_probe()
380 						       &phy->dpll_reset_reg)) {  in ti_pipe3_probe()
390 		clk = devm_clk_get(phy->dev, "dpll_ref");  in ti_pipe3_probe()
397 		clk = devm_clk_get(phy->dev, "dpll_ref_m2");  in ti_pipe3_probe()
404 		clk = devm_clk_get(phy->dev, "phy-div");  in ti_pipe3_probe()
411 		phy->div_clk = devm_clk_get(phy->dev, "div-clk");  in ti_pipe3_probe()
412 		if (IS_ERR(phy->div_clk)) {  in ti_pipe3_probe()
414 			return PTR_ERR(phy->div_clk);  in ti_pipe3_probe()
417 		phy->div_clk = ERR_PTR(-ENODEV);  in ti_pipe3_probe()
432 	phy->control_dev = &control_pdev->dev;  in ti_pipe3_probe()
434 	omap_control_phy_power(phy->control_dev, 0);  in ti_pipe3_probe()
436 	platform_set_drvdata(pdev, phy);  in ti_pipe3_probe()
437 	pm_runtime_enable(phy->dev);  in ti_pipe3_probe()
443 		if (!IS_ERR(phy->refclk)) {  in ti_pipe3_probe()
444 			clk_prepare_enable(phy->refclk);  in ti_pipe3_probe()
445 			phy->sata_refclk_enabled = true;  in ti_pipe3_probe()
449 	generic_phy = devm_phy_create(phy->dev, NULL, &ops);  in ti_pipe3_probe()
453 	phy_set_drvdata(generic_phy, phy);  in ti_pipe3_probe()
454 	phy_provider = devm_of_phy_provider_register(phy->dev,  in ti_pipe3_probe()
469 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)  in ti_pipe3_enable_clocks()  argument
473 	if (!IS_ERR(phy->refclk)) {  in ti_pipe3_enable_clocks()
474 		ret = clk_prepare_enable(phy->refclk);  in ti_pipe3_enable_clocks()
476 			dev_err(phy->dev, "Failed to enable refclk %d\n", ret);  in ti_pipe3_enable_clocks()
481 	if (!IS_ERR(phy->wkupclk)) {  in ti_pipe3_enable_clocks()
482 		ret = clk_prepare_enable(phy->wkupclk);  in ti_pipe3_enable_clocks()
484 			dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);  in ti_pipe3_enable_clocks()
489 	if (!IS_ERR(phy->div_clk)) {  in ti_pipe3_enable_clocks()
490 		ret = clk_prepare_enable(phy->div_clk);  in ti_pipe3_enable_clocks()
492 			dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);  in ti_pipe3_enable_clocks()
500 	if (!IS_ERR(phy->wkupclk))  in ti_pipe3_enable_clocks()
501 		clk_disable_unprepare(phy->wkupclk);  in ti_pipe3_enable_clocks()
504 	if (!IS_ERR(phy->refclk))  in ti_pipe3_enable_clocks()
505 		clk_disable_unprepare(phy->refclk);  in ti_pipe3_enable_clocks()
510 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)  in ti_pipe3_disable_clocks()  argument
512 	if (!IS_ERR(phy->wkupclk))  in ti_pipe3_disable_clocks()
513 		clk_disable_unprepare(phy->wkupclk);  in ti_pipe3_disable_clocks()
514 	if (!IS_ERR(phy->refclk)) {  in ti_pipe3_disable_clocks()
515 		clk_disable_unprepare(phy->refclk);  in ti_pipe3_disable_clocks()
520 		if (phy->sata_refclk_enabled) {  in ti_pipe3_disable_clocks()
521 			clk_disable_unprepare(phy->refclk);  in ti_pipe3_disable_clocks()
522 			phy->sata_refclk_enabled = false;  in ti_pipe3_disable_clocks()
526 	if (!IS_ERR(phy->div_clk))  in ti_pipe3_disable_clocks()
527 		clk_disable_unprepare(phy->div_clk);  in ti_pipe3_disable_clocks()