Lines Matching refs:dev_err
137 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); in ti_pipe3_get_dpll_params()
176 dev_err(phy->dev, "DPLL failed to lock\n"); in ti_pipe3_dpll_wait_lock()
283 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", in ti_pipe3_exit()
336 dev_err(&pdev->dev, "no DPLL data\n"); in ti_pipe3_probe()
348 dev_err(&pdev->dev, "unable to get sysclk\n"); in ti_pipe3_probe()
355 dev_err(&pdev->dev, "unable to get refclk\n"); in ti_pipe3_probe()
366 dev_err(&pdev->dev, "unable to get wkupclk\n"); in ti_pipe3_probe()
381 dev_err(&pdev->dev, in ti_pipe3_probe()
392 dev_err(&pdev->dev, "unable to get dpll ref clk\n"); in ti_pipe3_probe()
399 dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n"); in ti_pipe3_probe()
406 dev_err(&pdev->dev, "unable to get phy-div clk\n"); in ti_pipe3_probe()
413 dev_err(&pdev->dev, "unable to get div-clk\n"); in ti_pipe3_probe()
422 dev_err(&pdev->dev, "Failed to get control device phandle\n"); in ti_pipe3_probe()
428 dev_err(&pdev->dev, "Failed to get control device\n"); in ti_pipe3_probe()
476 dev_err(phy->dev, "Failed to enable refclk %d\n", ret); in ti_pipe3_enable_clocks()
484 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); in ti_pipe3_enable_clocks()
492 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); in ti_pipe3_enable_clocks()