209 	void __iomem *pipebase;  member
965 		|| (!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_pcie()
992 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */  in miphy28lp_init_pcie()
993 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */  in miphy28lp_init_pcie()
994 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */  in miphy28lp_init_pcie()
995 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */  in miphy28lp_init_pcie()
996 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */  in miphy28lp_init_pcie()
997 	writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */  in miphy28lp_init_pcie()
1008 	if ((!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_usb3()
1024 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);  in miphy28lp_init_usb3()
1025 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);  in miphy28lp_init_usb3()
1026 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);  in miphy28lp_init_usb3()
1027 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);  in miphy28lp_init_usb3()
1028 	writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);  in miphy28lp_init_usb3()
1029 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);  in miphy28lp_init_usb3()
1032 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);  in miphy28lp_init_usb3()
1033 	writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);  in miphy28lp_init_usb3()
1034 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);  in miphy28lp_init_usb3()
1035 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);  in miphy28lp_init_usb3()
1036 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);  in miphy28lp_init_usb3()
1037 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);  in miphy28lp_init_usb3()
1038 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);  in miphy28lp_init_usb3()
1039 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);  in miphy28lp_init_usb3()
1094 					     &miphy_phy->pipebase);  in miphy28lp_get_addr()