Lines Matching refs:BIT
23 #define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0)
24 #define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3)
25 #define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4)
26 #define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5)
33 #define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6)
34 #define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7)
35 #define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8)
41 #define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9)
42 #define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10)
47 #define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11)
48 #define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP BIT(12)
62 #define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
63 #define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON BIT(4)
64 #define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON BIT(7)
69 #define EXYNOS_4210_URSTCON_PHY0 BIT(0)
70 #define EXYNOS_4210_URSTCON_OTG_HLINK BIT(1)
71 #define EXYNOS_4210_URSTCON_OTG_PHYLINK BIT(2)
72 #define EXYNOS_4210_URSTCON_PHY1_ALL BIT(3)
73 #define EXYNOS_4210_URSTCON_PHY1_P0 BIT(4)
74 #define EXYNOS_4210_URSTCON_PHY1_P1P2 BIT(5)
75 #define EXYNOS_4210_URSTCON_HOST_LINK_ALL BIT(6)
76 #define EXYNOS_4210_URSTCON_HOST_LINK_P0 BIT(7)
77 #define EXYNOS_4210_URSTCON_HOST_LINK_P1 BIT(8)
78 #define EXYNOS_4210_URSTCON_HOST_LINK_P2 BIT(9)
82 #define EXYNOS_4210_USB_ISOL_DEVICE BIT(0)
84 #define EXYNOS_4210_USB_ISOL_HOST BIT(0)