Lines Matching refs:dev
65 static int find_anything(struct device *dev, void *data) in find_anything() argument
77 struct device *dev; in no_pci_devices() local
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); in no_pci_devices()
81 no_devices = (dev == NULL); in no_pci_devices()
82 put_device(dev); in no_pci_devices()
90 static void release_pcibus_dev(struct device *dev) in release_pcibus_dev() argument
92 struct pci_bus *pci_bus = to_pci_bus(dev); in release_pcibus_dev()
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) in decode_bar() argument
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, in __pci_read_base() argument
185 if (!dev->mmio_always_on) { in __pci_read_base()
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); in __pci_read_base()
188 pci_write_config_word(dev, PCI_COMMAND, in __pci_read_base()
193 res->name = pci_name(dev); in __pci_read_base()
195 pci_read_config_dword(dev, pos, &l); in __pci_read_base()
196 pci_write_config_dword(dev, pos, l | mask); in __pci_read_base()
197 pci_read_config_dword(dev, pos, &sz); in __pci_read_base()
198 pci_write_config_dword(dev, pos, l); in __pci_read_base()
217 res->flags = decode_bar(dev, l); in __pci_read_base()
236 pci_read_config_dword(dev, pos + 4, &l); in __pci_read_base()
237 pci_write_config_dword(dev, pos + 4, ~0); in __pci_read_base()
238 pci_read_config_dword(dev, pos + 4, &sz); in __pci_read_base()
239 pci_write_config_dword(dev, pos + 4, l); in __pci_read_base()
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); in __pci_read_base()
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", in __pci_read_base()
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", in __pci_read_base()
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", in __pci_read_base()
284 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", in __pci_read_base()
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); in __pci_read_base()
318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) in pci_read_bases() argument
322 if (dev->non_compliant_bars) in pci_read_bases()
326 struct resource *res = &dev->resource[pos]; in pci_read_bases()
328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); in pci_read_bases()
332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
333 dev->rom_base_reg = rom; in pci_read_bases()
336 __pci_read_base(dev, pci_bar_mem32, res, rom); in pci_read_bases()
342 struct pci_dev *dev = child->self; in pci_read_bridge_io() local
350 if (dev->io_window_1k) { in pci_read_bridge_io()
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); in pci_read_bridge_io()
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); in pci_read_bridge_io()
365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); in pci_read_bridge_io()
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); in pci_read_bridge_io()
375 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); in pci_read_bridge_io()
382 struct pci_dev *dev = child->self; in pci_read_bridge_mmio() local
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); in pci_read_bridge_mmio()
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); in pci_read_bridge_mmio()
397 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); in pci_read_bridge_mmio()
404 struct pci_dev *dev = child->self; in pci_read_bridge_mmio_pref() local
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); in pci_read_bridge_mmio_pref()
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); in pci_read_bridge_mmio_pref()
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); in pci_read_bridge_mmio_pref()
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); in pci_read_bridge_mmio_pref()
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", in pci_read_bridge_mmio_pref()
450 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); in pci_read_bridge_mmio_pref()
457 struct pci_dev *dev = child->self; in pci_read_bridge_bases() local
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n", in pci_read_bridge_bases()
466 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
476 if (dev->transparent) { in pci_read_bridge_bases()
481 dev_printk(KERN_DEBUG, &dev->dev, in pci_read_bridge_bases()
511 static void pci_release_host_bridge_dev(struct device *dev) in pci_release_host_bridge_dev() argument
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); in pci_release_host_bridge_dev()
694 d = dev_get_msi_domain(&b->self->dev); in pci_set_bus_msi_domain()
700 dev_set_msi_domain(&bus->dev, d); in pci_set_bus_msi_domain()
726 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
727 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
738 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
743 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
744 child->dev.parent = child->bridge; in pci_alloc_child_bus()
757 ret = device_register(&child->dev); in pci_alloc_child_bus()
768 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, in pci_add_new_bus() argument
773 child = pci_alloc_child_bus(parent, dev, busnr); in pci_add_new_bus()
804 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) in pci_scan_bridge() argument
807 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge()
813 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); in pci_scan_bridge()
818 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge()
822 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); in pci_scan_bridge()
830 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge()
837 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); in pci_scan_bridge()
838 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, in pci_scan_bridge()
841 pci_enable_crs(dev); in pci_scan_bridge()
861 child = pci_add_new_bus(bus, dev, secondary); in pci_scan_bridge()
871 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", in pci_scan_bridge()
889 pci_write_config_dword(dev, PCI_PRIMARY_BUS, in pci_scan_bridge()
895 pci_write_config_word(dev, PCI_STATUS, 0xffff); in pci_scan_bridge()
902 child = pci_add_new_bus(bus, dev, max+1); in pci_scan_bridge()
925 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); in pci_scan_bridge()
965 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); in pci_scan_bridge()
978 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n", in pci_scan_bridge()
984 dev_name(&bus->dev), in pci_scan_bridge()
991 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); in pci_scan_bridge()
1001 static void pci_read_irq(struct pci_dev *dev) in pci_read_irq() argument
1005 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); in pci_read_irq()
1006 dev->pin = irq; in pci_read_irq()
1008 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); in pci_read_irq()
1009 dev->irq = irq; in pci_read_irq()
1075 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) in pci_ext_cfg_is_aliased() argument
1081 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); in pci_ext_cfg_is_aliased()
1085 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL in pci_ext_cfg_is_aliased()
1107 static int pci_cfg_space_size_ext(struct pci_dev *dev) in pci_cfg_space_size_ext() argument
1112 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) in pci_cfg_space_size_ext()
1114 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) in pci_cfg_space_size_ext()
1123 int pci_cfg_space_size(struct pci_dev *dev) in pci_cfg_space_size() argument
1129 class = dev->class >> 8; in pci_cfg_space_size()
1131 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1133 if (!pci_is_pcie(dev)) { in pci_cfg_space_size()
1134 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pci_cfg_space_size()
1138 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); in pci_cfg_space_size()
1143 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1151 void pci_msi_setup_pci_dev(struct pci_dev *dev) in pci_msi_setup_pci_dev() argument
1158 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); in pci_msi_setup_pci_dev()
1159 if (dev->msi_cap) in pci_msi_setup_pci_dev()
1160 pci_msi_set_enable(dev, 0); in pci_msi_setup_pci_dev()
1162 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); in pci_msi_setup_pci_dev()
1163 if (dev->msix_cap) in pci_msi_setup_pci_dev()
1164 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); in pci_msi_setup_pci_dev()
1177 int pci_setup_device(struct pci_dev *dev) in pci_setup_device() argument
1186 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) in pci_setup_device()
1189 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1190 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1191 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1192 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1193 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1194 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1195 set_pcie_port_type(dev); in pci_setup_device()
1197 pci_dev_assign_slot(dev); in pci_setup_device()
1200 dev->dma_mask = 0xffffffff; in pci_setup_device()
1202 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1203 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1204 PCI_FUNC(dev->devfn)); in pci_setup_device()
1206 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); in pci_setup_device()
1207 dev->revision = class & 0xff; in pci_setup_device()
1208 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1210 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", in pci_setup_device()
1211 dev->vendor, dev->device, dev->hdr_type, dev->class); in pci_setup_device()
1214 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1217 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1219 pci_msi_setup_pci_dev(dev); in pci_setup_device()
1222 pci_fixup_device(pci_fixup_early, dev); in pci_setup_device()
1224 class = dev->class >> 8; in pci_setup_device()
1226 if (dev->non_compliant_bars) { in pci_setup_device()
1227 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_setup_device()
1229 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1232 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_setup_device()
1236 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1240 pci_read_irq(dev); in pci_setup_device()
1241 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); in pci_setup_device()
1242 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1243 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
1253 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); in pci_setup_device()
1257 res = &dev->resource[0]; in pci_setup_device()
1259 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1260 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", in pci_setup_device()
1264 res = &dev->resource[1]; in pci_setup_device()
1266 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1267 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", in pci_setup_device()
1273 res = &dev->resource[2]; in pci_setup_device()
1275 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1276 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", in pci_setup_device()
1280 res = &dev->resource[3]; in pci_setup_device()
1282 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1283 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", in pci_setup_device()
1295 pci_read_irq(dev); in pci_setup_device()
1296 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
1297 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); in pci_setup_device()
1298 set_pcie_hotplug_bridge(dev); in pci_setup_device()
1299 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); in pci_setup_device()
1301 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1302 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
1309 pci_read_irq(dev); in pci_setup_device()
1310 pci_read_bases(dev, 1, 0); in pci_setup_device()
1311 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1312 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
1316 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", in pci_setup_device()
1317 dev->hdr_type); in pci_setup_device()
1321 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", in pci_setup_device()
1322 dev->class, dev->hdr_type); in pci_setup_device()
1323 dev->class = PCI_CLASS_NOT_DEFINED << 8; in pci_setup_device()
1330 static void pci_configure_mps(struct pci_dev *dev) in pci_configure_mps() argument
1332 struct pci_dev *bridge = pci_upstream_bridge(dev); in pci_configure_mps()
1335 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) in pci_configure_mps()
1338 mps = pcie_get_mps(dev); in pci_configure_mps()
1345 …dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_… in pci_configure_mps()
1357 rc = pcie_set_mps(dev, p_mps); in pci_configure_mps()
1359 …dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and… in pci_configure_mps()
1364 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n", in pci_configure_mps()
1365 p_mps, mps, 128 << dev->pcie_mpss); in pci_configure_mps()
1376 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) in program_hpp_type0() argument
1384 dev_warn(&dev->dev, in program_hpp_type0()
1390 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); in program_hpp_type0()
1391 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); in program_hpp_type0()
1392 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); in program_hpp_type0()
1397 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); in program_hpp_type0()
1400 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in program_hpp_type0()
1401 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, in program_hpp_type0()
1403 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); in program_hpp_type0()
1408 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); in program_hpp_type0()
1412 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) in program_hpp_type1() argument
1415 dev_warn(&dev->dev, "PCI-X settings not supported\n"); in program_hpp_type1()
1418 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) in program_hpp_type2() argument
1427 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", in program_hpp_type2()
1443 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, in program_hpp_type2()
1447 if (pcie_cap_has_lnkctl(dev)) in program_hpp_type2()
1448 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, in program_hpp_type2()
1452 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); in program_hpp_type2()
1457 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); in program_hpp_type2()
1459 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpp_type2()
1462 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); in program_hpp_type2()
1464 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpp_type2()
1467 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); in program_hpp_type2()
1469 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpp_type2()
1472 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); in program_hpp_type2()
1474 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); in program_hpp_type2()
1484 static void pci_configure_device(struct pci_dev *dev) in pci_configure_device() argument
1489 pci_configure_mps(dev); in pci_configure_device()
1492 ret = pci_get_hp_params(dev, &hpp); in pci_configure_device()
1496 program_hpp_type2(dev, hpp.t2); in pci_configure_device()
1497 program_hpp_type1(dev, hpp.t1); in pci_configure_device()
1498 program_hpp_type0(dev, hpp.t0); in pci_configure_device()
1501 static void pci_release_capabilities(struct pci_dev *dev) in pci_release_capabilities() argument
1503 pci_vpd_release(dev); in pci_release_capabilities()
1504 pci_iov_release(dev); in pci_release_capabilities()
1505 pci_free_cap_save_buffers(dev); in pci_release_capabilities()
1515 static void pci_release_dev(struct device *dev) in pci_release_dev() argument
1519 pci_dev = to_pci_dev(dev); in pci_release_dev()
1530 struct pci_dev *dev; in pci_alloc_dev() local
1532 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); in pci_alloc_dev()
1533 if (!dev) in pci_alloc_dev()
1536 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
1537 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
1538 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
1540 return dev; in pci_alloc_dev()
1590 struct pci_dev *dev; in pci_scan_device() local
1596 dev = pci_alloc_dev(bus); in pci_scan_device()
1597 if (!dev) in pci_scan_device()
1600 dev->devfn = devfn; in pci_scan_device()
1601 dev->vendor = l & 0xffff; in pci_scan_device()
1602 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
1604 pci_set_of_node(dev); in pci_scan_device()
1606 if (pci_setup_device(dev)) { in pci_scan_device()
1607 pci_bus_put(dev->bus); in pci_scan_device()
1608 kfree(dev); in pci_scan_device()
1612 return dev; in pci_scan_device()
1615 static void pci_init_capabilities(struct pci_dev *dev) in pci_init_capabilities() argument
1618 pci_ea_init(dev); in pci_init_capabilities()
1621 pci_msi_init_pci_dev(dev); in pci_init_capabilities()
1624 pci_allocate_cap_save_buffers(dev); in pci_init_capabilities()
1627 pci_pm_init(dev); in pci_init_capabilities()
1630 pci_vpd_pci22_init(dev); in pci_init_capabilities()
1633 pci_configure_ari(dev); in pci_init_capabilities()
1636 pci_iov_init(dev); in pci_init_capabilities()
1639 pci_ats_init(dev); in pci_init_capabilities()
1642 pci_enable_acs(dev); in pci_init_capabilities()
1644 pci_cleanup_aer_error_status_regs(dev); in pci_init_capabilities()
1652 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) in pci_dev_msi_domain() argument
1660 d = dev_get_msi_domain(&dev->dev); in pci_dev_msi_domain()
1668 d = pci_msi_get_device_domain(dev); in pci_dev_msi_domain()
1675 static void pci_set_msi_domain(struct pci_dev *dev) in pci_set_msi_domain() argument
1684 d = pci_dev_msi_domain(dev); in pci_set_msi_domain()
1686 d = dev_get_msi_domain(&dev->bus->dev); in pci_set_msi_domain()
1688 dev_set_msi_domain(&dev->dev, d); in pci_set_msi_domain()
1698 static void pci_dma_configure(struct pci_dev *dev) in pci_dma_configure() argument
1700 struct device *bridge = pci_get_host_bridge_device(dev); in pci_dma_configure()
1704 of_dma_configure(&dev->dev, bridge->parent->of_node); in pci_dma_configure()
1710 dev_warn(&dev->dev, "DMA not supported.\n"); in pci_dma_configure()
1712 arch_setup_dma_ops(&dev->dev, 0, 0, NULL, in pci_dma_configure()
1719 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) in pci_device_add() argument
1723 pci_configure_device(dev); in pci_device_add()
1725 device_initialize(&dev->dev); in pci_device_add()
1726 dev->dev.release = pci_release_dev; in pci_device_add()
1728 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
1729 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
1730 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
1731 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
1732 pci_dma_configure(dev); in pci_device_add()
1734 pci_set_dma_max_seg_size(dev, 65536); in pci_device_add()
1735 pci_set_dma_seg_boundary(dev, 0xffffffff); in pci_device_add()
1738 pci_fixup_device(pci_fixup_header, dev); in pci_device_add()
1741 pci_reassigndev_resource_alignment(dev); in pci_device_add()
1744 dev->state_saved = false; in pci_device_add()
1747 pci_init_capabilities(dev); in pci_device_add()
1754 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
1757 ret = pcibios_add_device(dev); in pci_device_add()
1761 pci_set_msi_domain(dev); in pci_device_add()
1764 dev->match_driver = false; in pci_device_add()
1765 ret = device_add(&dev->dev); in pci_device_add()
1771 struct pci_dev *dev; in pci_scan_single_device() local
1773 dev = pci_get_slot(bus, devfn); in pci_scan_single_device()
1774 if (dev) { in pci_scan_single_device()
1775 pci_dev_put(dev); in pci_scan_single_device()
1776 return dev; in pci_scan_single_device()
1779 dev = pci_scan_device(bus, devfn); in pci_scan_single_device()
1780 if (!dev) in pci_scan_single_device()
1783 pci_device_add(dev, bus); in pci_scan_single_device()
1785 return dev; in pci_scan_single_device()
1789 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) in next_fn() argument
1796 if (!dev) in next_fn()
1798 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); in next_fn()
1802 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); in next_fn()
1811 if (!dev || dev->multifunction) in next_fn()
1845 struct pci_dev *dev; in pci_scan_slot() local
1850 dev = pci_scan_single_device(bus, devfn); in pci_scan_slot()
1851 if (!dev) in pci_scan_slot()
1853 if (!dev->is_added) in pci_scan_slot()
1856 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { in pci_scan_slot()
1857 dev = pci_scan_single_device(bus, devfn + fn); in pci_scan_slot()
1858 if (dev) { in pci_scan_slot()
1859 if (!dev->is_added) in pci_scan_slot()
1861 dev->multifunction = 1; in pci_scan_slot()
1873 static int pcie_find_smpss(struct pci_dev *dev, void *data) in pcie_find_smpss() argument
1877 if (!pci_is_pcie(dev)) in pcie_find_smpss()
1895 if (dev->is_hotplug_bridge && in pcie_find_smpss()
1896 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pcie_find_smpss()
1899 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
1900 *smpss = dev->pcie_mpss; in pcie_find_smpss()
1905 static void pcie_write_mps(struct pci_dev *dev, int mps) in pcie_write_mps() argument
1910 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
1912 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && in pcie_write_mps()
1913 dev->bus->self) in pcie_write_mps()
1926 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
1929 rc = pcie_set_mps(dev, mps); in pcie_write_mps()
1931 dev_err(&dev->dev, "Failed attempting to set the MPS\n"); in pcie_write_mps()
1934 static void pcie_write_mrrs(struct pci_dev *dev) in pcie_write_mrrs() argument
1949 mrrs = pcie_get_mps(dev); in pcie_write_mrrs()
1956 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { in pcie_write_mrrs()
1957 rc = pcie_set_readrq(dev, mrrs); in pcie_write_mrrs()
1961 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); in pcie_write_mrrs()
1966 …dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienc… in pcie_write_mrrs()
1969 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) in pcie_bus_configure_set() argument
1973 if (!pci_is_pcie(dev)) in pcie_bus_configure_set()
1981 orig_mps = pcie_get_mps(dev); in pcie_bus_configure_set()
1983 pcie_write_mps(dev, mps); in pcie_bus_configure_set()
1984 pcie_write_mrrs(dev); in pcie_bus_configure_set()
1986 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", in pcie_bus_configure_set()
1987 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
1988 orig_mps, pcie_get_readrq(dev)); in pcie_bus_configure_set()
2029 struct pci_dev *dev; in pci_scan_child_bus() local
2031 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus()
2045 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus()
2051 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_scan_child_bus()
2052 if (pci_is_bridge(dev)) in pci_scan_child_bus()
2053 max = pci_scan_bridge(bus, dev, max, pass); in pci_scan_child_bus()
2063 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus()
2111 dev_dbg(&b2->dev, "bus already known\n"); in pci_create_root_bus()
2119 bridge->dev.parent = parent; in pci_create_root_bus()
2120 bridge->dev.release = pci_release_host_bridge_dev; in pci_create_root_bus()
2121 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); in pci_create_root_bus()
2128 error = device_register(&bridge->dev); in pci_create_root_bus()
2130 put_device(&bridge->dev); in pci_create_root_bus()
2133 b->bridge = get_device(&bridge->dev); in pci_create_root_bus()
2141 b->dev.class = &pcibus_class; in pci_create_root_bus()
2142 b->dev.parent = b->bridge; in pci_create_root_bus()
2143 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); in pci_create_root_bus()
2144 error = device_register(&b->dev); in pci_create_root_bus()
2154 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); in pci_create_root_bus()
2156 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); in pci_create_root_bus()
2177 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); in pci_create_root_bus()
2187 put_device(&bridge->dev); in pci_create_root_bus()
2188 device_unregister(&bridge->dev); in pci_create_root_bus()
2214 dev_printk(KERN_DEBUG, &b->dev, in pci_bus_insert_busn_res()
2234 dev_printk(KERN_DEBUG, &b->dev, in pci_bus_update_busn_res_end()
2253 dev_printk(KERN_DEBUG, &b->dev, in pci_bus_release_busn_res()
2280 dev_info(&b->dev, in pci_scan_root_bus_msi()