Lines Matching refs:dev
54 struct pci_dev *dev; member
59 static void pci_dev_d3_sleep(struct pci_dev *dev) in pci_dev_d3_sleep() argument
61 unsigned int delay = dev->d3_delay; in pci_dev_d3_sleep()
136 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); in pci_ioremap_bar()
191 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) in pci_find_next_capability() argument
193 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
237 int pci_find_capability(struct pci_dev *dev, int cap) in pci_find_capability() argument
241 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
243 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
288 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) in pci_find_next_ext_capability() argument
297 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
303 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) in pci_find_next_ext_capability()
321 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) in pci_find_next_ext_capability()
343 int pci_find_ext_capability(struct pci_dev *dev, int cap) in pci_find_ext_capability() argument
345 return pci_find_next_ext_capability(dev, 0, cap); in pci_find_ext_capability()
349 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) in __pci_find_next_ht_cap() argument
359 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
362 rc = pci_read_config_byte(dev, pos + 3, &cap); in __pci_find_next_ht_cap()
369 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
389 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) in pci_find_next_ht_capability() argument
391 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); in pci_find_next_ht_capability()
406 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) in pci_find_ht_capability() argument
410 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
412 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); in pci_find_ht_capability()
426 struct resource *pci_find_parent_resource(const struct pci_dev *dev, in pci_find_parent_resource() argument
429 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
468 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) in pci_find_pcie_root_port() argument
472 bridge = pci_upstream_bridge(dev); in pci_find_pcie_root_port()
493 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) in pci_wait_for_pending() argument
503 pci_read_config_word(dev, pos, &status); in pci_wait_for_pending()
518 static void pci_restore_bars(struct pci_dev *dev) in pci_restore_bars() argument
523 if (dev->is_virtfn) in pci_restore_bars()
527 pci_update_resource(dev, i); in pci_restore_bars()
541 static inline bool platform_pci_power_manageable(struct pci_dev *dev) in platform_pci_power_manageable() argument
543 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; in platform_pci_power_manageable()
546 static inline int platform_pci_set_power_state(struct pci_dev *dev, in platform_pci_set_power_state() argument
549 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; in platform_pci_set_power_state()
552 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) in platform_pci_choose_state() argument
555 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; in platform_pci_choose_state()
558 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) in platform_pci_sleep_wake() argument
561 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; in platform_pci_sleep_wake()
564 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) in platform_pci_run_wake() argument
567 pci_platform_pm->run_wake(dev, enable) : -ENODEV; in platform_pci_run_wake()
570 static inline bool platform_pci_need_resume(struct pci_dev *dev) in platform_pci_need_resume() argument
572 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; in platform_pci_need_resume()
588 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_raw_set_power_state() argument
594 if (dev->current_state == state) in pci_raw_set_power_state()
597 if (!dev->pm_cap) in pci_raw_set_power_state()
607 if (state != PCI_D0 && dev->current_state <= PCI_D3cold in pci_raw_set_power_state()
608 && dev->current_state > state) { in pci_raw_set_power_state()
609 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", in pci_raw_set_power_state()
610 dev->current_state, state); in pci_raw_set_power_state()
615 if ((state == PCI_D1 && !dev->d1_support) in pci_raw_set_power_state()
616 || (state == PCI_D2 && !dev->d2_support)) in pci_raw_set_power_state()
619 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_raw_set_power_state()
625 switch (dev->current_state) { in pci_raw_set_power_state()
645 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_raw_set_power_state()
649 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) in pci_raw_set_power_state()
650 pci_dev_d3_sleep(dev); in pci_raw_set_power_state()
651 else if (state == PCI_D2 || dev->current_state == PCI_D2) in pci_raw_set_power_state()
654 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_raw_set_power_state()
655 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_raw_set_power_state()
656 if (dev->current_state != state && printk_ratelimit()) in pci_raw_set_power_state()
657 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", in pci_raw_set_power_state()
658 dev->current_state); in pci_raw_set_power_state()
674 pci_restore_bars(dev); in pci_raw_set_power_state()
676 if (dev->bus->self) in pci_raw_set_power_state()
677 pcie_aspm_pm_state_change(dev->bus->self); in pci_raw_set_power_state()
688 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) in pci_update_current_state() argument
690 if (dev->pm_cap) { in pci_update_current_state()
697 if (dev->current_state == PCI_D3cold) in pci_update_current_state()
700 dev->current_state = PCI_D3cold; in pci_update_current_state()
703 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
704 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_update_current_state()
706 dev->current_state = state; in pci_update_current_state()
714 void pci_power_up(struct pci_dev *dev) in pci_power_up() argument
716 if (platform_pci_power_manageable(dev)) in pci_power_up()
717 platform_pci_set_power_state(dev, PCI_D0); in pci_power_up()
719 pci_raw_set_power_state(dev, PCI_D0); in pci_power_up()
720 pci_update_current_state(dev, PCI_D0); in pci_power_up()
728 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) in pci_platform_power_transition() argument
732 if (platform_pci_power_manageable(dev)) { in pci_platform_power_transition()
733 error = platform_pci_set_power_state(dev, state); in pci_platform_power_transition()
735 pci_update_current_state(dev, state); in pci_platform_power_transition()
739 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
740 dev->current_state = PCI_D0; in pci_platform_power_transition()
753 pm_request_resume(&pci_dev->dev); in pci_wakeup()
772 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) in __pci_start_power_transition() argument
775 pci_platform_power_transition(dev, PCI_D0); in __pci_start_power_transition()
783 if (dev->runtime_d3cold) { in __pci_start_power_transition()
784 msleep(dev->d3cold_delay); in __pci_start_power_transition()
791 pci_wakeup_bus(dev->subordinate); in __pci_start_power_transition()
801 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) in __pci_dev_set_current_state() argument
805 dev->current_state = state; in __pci_dev_set_current_state()
827 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) in __pci_complete_power_transition() argument
833 ret = pci_platform_power_transition(dev, state); in __pci_complete_power_transition()
836 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); in __pci_complete_power_transition()
856 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_set_power_state() argument
865 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) in pci_set_power_state()
874 if (dev->current_state == state) in pci_set_power_state()
877 __pci_start_power_transition(dev, state); in pci_set_power_state()
881 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in pci_set_power_state()
888 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? in pci_set_power_state()
891 if (!__pci_complete_power_transition(dev, state)) in pci_set_power_state()
908 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) in pci_choose_state() argument
912 if (!dev->pm_cap) in pci_choose_state()
915 ret = platform_pci_choose_state(dev); in pci_choose_state()
929 dev_info(&dev->dev, "unrecognized suspend event %d\n", in pci_choose_state()
951 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) in pci_find_saved_cap() argument
953 return _pci_find_saved_cap(dev, cap, false); in pci_find_saved_cap()
956 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) in pci_find_saved_ext_cap() argument
958 return _pci_find_saved_cap(dev, cap, true); in pci_find_saved_ext_cap()
961 static int pci_save_pcie_state(struct pci_dev *dev) in pci_save_pcie_state() argument
967 if (!pci_is_pcie(dev)) in pci_save_pcie_state()
970 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); in pci_save_pcie_state()
972 dev_err(&dev->dev, "buffer not found in %s\n", __func__); in pci_save_pcie_state()
977 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); in pci_save_pcie_state()
978 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); in pci_save_pcie_state()
979 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); in pci_save_pcie_state()
980 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); in pci_save_pcie_state()
981 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); in pci_save_pcie_state()
982 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); in pci_save_pcie_state()
983 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); in pci_save_pcie_state()
988 static void pci_restore_pcie_state(struct pci_dev *dev) in pci_restore_pcie_state() argument
994 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); in pci_restore_pcie_state()
999 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); in pci_restore_pcie_state()
1000 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); in pci_restore_pcie_state()
1001 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); in pci_restore_pcie_state()
1002 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); in pci_restore_pcie_state()
1003 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); in pci_restore_pcie_state()
1004 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); in pci_restore_pcie_state()
1005 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); in pci_restore_pcie_state()
1009 static int pci_save_pcix_state(struct pci_dev *dev) in pci_save_pcix_state() argument
1014 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pci_save_pcix_state()
1018 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); in pci_save_pcix_state()
1020 dev_err(&dev->dev, "buffer not found in %s\n", __func__); in pci_save_pcix_state()
1024 pci_read_config_word(dev, pos + PCI_X_CMD, in pci_save_pcix_state()
1030 static void pci_restore_pcix_state(struct pci_dev *dev) in pci_restore_pcix_state() argument
1036 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); in pci_restore_pcix_state()
1037 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pci_restore_pcix_state()
1042 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); in pci_restore_pcix_state()
1050 int pci_save_state(struct pci_dev *dev) in pci_save_state() argument
1055 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1056 dev->state_saved = true; in pci_save_state()
1058 i = pci_save_pcie_state(dev); in pci_save_state()
1062 i = pci_save_pcix_state(dev); in pci_save_state()
1066 return pci_save_vc_state(dev); in pci_save_state()
1080 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", in pci_restore_config_dword()
1121 void pci_restore_state(struct pci_dev *dev) in pci_restore_state() argument
1123 if (!dev->state_saved) in pci_restore_state()
1127 pci_restore_pcie_state(dev); in pci_restore_state()
1128 pci_restore_ats_state(dev); in pci_restore_state()
1129 pci_restore_vc_state(dev); in pci_restore_state()
1131 pci_cleanup_aer_error_status_regs(dev); in pci_restore_state()
1133 pci_restore_config_space(dev); in pci_restore_state()
1135 pci_restore_pcix_state(dev); in pci_restore_state()
1136 pci_restore_msi_state(dev); in pci_restore_state()
1139 pci_enable_acs(dev); in pci_restore_state()
1140 pci_restore_iov_state(dev); in pci_restore_state()
1142 dev->state_saved = false; in pci_restore_state()
1158 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) in pci_store_saved_state() argument
1165 if (!dev->state_saved) in pci_store_saved_state()
1170 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1177 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1181 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1197 int pci_load_saved_state(struct pci_dev *dev, in pci_load_saved_state() argument
1202 dev->state_saved = false; in pci_load_saved_state()
1207 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1214 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1223 dev->state_saved = true; in pci_load_saved_state()
1234 int pci_load_and_free_saved_state(struct pci_dev *dev, in pci_load_and_free_saved_state() argument
1237 int ret = pci_load_saved_state(dev, *state); in pci_load_and_free_saved_state()
1244 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) in pcibios_enable_device() argument
1246 return pci_enable_resources(dev, bars); in pcibios_enable_device()
1249 static int do_pci_enable_device(struct pci_dev *dev, int bars) in do_pci_enable_device() argument
1256 err = pci_set_power_state(dev, PCI_D0); in do_pci_enable_device()
1260 bridge = pci_upstream_bridge(dev); in do_pci_enable_device()
1264 err = pcibios_enable_device(dev, bars); in do_pci_enable_device()
1267 pci_fixup_device(pci_fixup_enable, dev); in do_pci_enable_device()
1269 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
1272 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in do_pci_enable_device()
1274 pci_read_config_word(dev, PCI_COMMAND, &cmd); in do_pci_enable_device()
1276 pci_write_config_word(dev, PCI_COMMAND, in do_pci_enable_device()
1290 int pci_reenable_device(struct pci_dev *dev) in pci_reenable_device() argument
1292 if (pci_is_enabled(dev)) in pci_reenable_device()
1293 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
1298 static void pci_enable_bridge(struct pci_dev *dev) in pci_enable_bridge() argument
1303 bridge = pci_upstream_bridge(dev); in pci_enable_bridge()
1307 if (pci_is_enabled(dev)) { in pci_enable_bridge()
1308 if (!dev->is_busmaster) in pci_enable_bridge()
1309 pci_set_master(dev); in pci_enable_bridge()
1313 retval = pci_enable_device(dev); in pci_enable_bridge()
1315 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", in pci_enable_bridge()
1317 pci_set_master(dev); in pci_enable_bridge()
1320 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) in pci_enable_device_flags() argument
1332 if (dev->pm_cap) { in pci_enable_device_flags()
1334 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_enable_device_flags()
1335 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_enable_device_flags()
1338 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
1341 bridge = pci_upstream_bridge(dev); in pci_enable_device_flags()
1347 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
1350 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
1353 err = do_pci_enable_device(dev, bars); in pci_enable_device_flags()
1355 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
1367 int pci_enable_device_io(struct pci_dev *dev) in pci_enable_device_io() argument
1369 return pci_enable_device_flags(dev, IORESOURCE_IO); in pci_enable_device_io()
1381 int pci_enable_device_mem(struct pci_dev *dev) in pci_enable_device_mem() argument
1383 return pci_enable_device_flags(dev, IORESOURCE_MEM); in pci_enable_device_mem()
1398 int pci_enable_device(struct pci_dev *dev) in pci_enable_device() argument
1400 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); in pci_enable_device()
1420 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); in pcim_release() local
1424 if (dev->msi_enabled) in pcim_release()
1425 pci_disable_msi(dev); in pcim_release()
1426 if (dev->msix_enabled) in pcim_release()
1427 pci_disable_msix(dev); in pcim_release()
1431 pci_release_region(dev, i); in pcim_release()
1434 pci_intx(dev, this->orig_intx); in pcim_release()
1437 pci_disable_device(dev); in pcim_release()
1444 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
1451 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
1457 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
1514 int __weak pcibios_add_device(struct pci_dev *dev) in pcibios_add_device() argument
1527 void __weak pcibios_release_device(struct pci_dev *dev) {} in pcibios_release_device() argument
1537 void __weak pcibios_disable_device (struct pci_dev *dev) {} in pcibios_disable_device() argument
1550 static void do_pci_disable_device(struct pci_dev *dev) in do_pci_disable_device() argument
1554 pci_read_config_word(dev, PCI_COMMAND, &pci_command); in do_pci_disable_device()
1557 pci_write_config_word(dev, PCI_COMMAND, pci_command); in do_pci_disable_device()
1560 pcibios_disable_device(dev); in do_pci_disable_device()
1570 void pci_disable_enabled_device(struct pci_dev *dev) in pci_disable_enabled_device() argument
1572 if (pci_is_enabled(dev)) in pci_disable_enabled_device()
1573 do_pci_disable_device(dev); in pci_disable_enabled_device()
1586 void pci_disable_device(struct pci_dev *dev) in pci_disable_device() argument
1590 dr = find_pci_dr(dev); in pci_disable_device()
1594 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
1597 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
1600 do_pci_disable_device(dev); in pci_disable_device()
1602 dev->is_busmaster = 0; in pci_disable_device()
1615 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, in pcibios_set_pcie_reset_state() argument
1629 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) in pci_set_pcie_reset_state() argument
1631 return pcibios_set_pcie_reset_state(dev, state); in pci_set_pcie_reset_state()
1643 bool pci_check_pme_status(struct pci_dev *dev) in pci_check_pme_status() argument
1649 if (!dev->pm_cap) in pci_check_pme_status()
1652 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
1653 pci_read_config_word(dev, pmcsr_pos, &pmcsr); in pci_check_pme_status()
1665 pci_write_config_word(dev, pmcsr_pos, pmcsr); in pci_check_pme_status()
1678 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) in pci_pme_wakeup() argument
1680 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
1681 dev->pme_poll = false; in pci_pme_wakeup()
1683 if (pci_check_pme_status(dev)) { in pci_pme_wakeup()
1684 pci_wakeup_event(dev); in pci_pme_wakeup()
1685 pm_request_resume(&dev->dev); in pci_pme_wakeup()
1706 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) in pci_pme_capable() argument
1708 if (!dev->pm_cap) in pci_pme_capable()
1711 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
1721 if (pme_dev->dev->pme_poll) { in pci_pme_list_scan()
1724 bridge = pme_dev->dev->bus->self; in pci_pme_list_scan()
1732 pci_pme_wakeup(pme_dev->dev, NULL); in pci_pme_list_scan()
1744 static void __pci_pme_active(struct pci_dev *dev, bool enable) in __pci_pme_active() argument
1748 if (!dev->pme_support) in __pci_pme_active()
1751 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
1757 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
1768 void pci_pme_active(struct pci_dev *dev, bool enable) in pci_pme_active() argument
1770 __pci_pme_active(dev, enable); in pci_pme_active()
1792 if (dev->pme_poll) { in pci_pme_active()
1798 dev_warn(&dev->dev, "can't enable PME#\n"); in pci_pme_active()
1801 pme_dev->dev = dev; in pci_pme_active()
1811 if (pme_dev->dev == dev) { in pci_pme_active()
1821 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); in pci_pme_active()
1845 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, in __pci_enable_wake() argument
1850 if (enable && !runtime && !device_may_wakeup(&dev->dev)) in __pci_enable_wake()
1854 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
1866 if (pci_pme_capable(dev, state)) in __pci_enable_wake()
1867 pci_pme_active(dev, true); in __pci_enable_wake()
1870 error = runtime ? platform_pci_run_wake(dev, true) : in __pci_enable_wake()
1871 platform_pci_sleep_wake(dev, true); in __pci_enable_wake()
1875 dev->wakeup_prepared = true; in __pci_enable_wake()
1878 platform_pci_run_wake(dev, false); in __pci_enable_wake()
1880 platform_pci_sleep_wake(dev, false); in __pci_enable_wake()
1881 pci_pme_active(dev, false); in __pci_enable_wake()
1882 dev->wakeup_prepared = false; in __pci_enable_wake()
1903 int pci_wake_from_d3(struct pci_dev *dev, bool enable) in pci_wake_from_d3() argument
1905 return pci_pme_capable(dev, PCI_D3cold) ? in pci_wake_from_d3()
1906 pci_enable_wake(dev, PCI_D3cold, enable) : in pci_wake_from_d3()
1907 pci_enable_wake(dev, PCI_D3hot, enable); in pci_wake_from_d3()
1919 static pci_power_t pci_target_state(struct pci_dev *dev) in pci_target_state() argument
1923 if (platform_pci_power_manageable(dev)) { in pci_target_state()
1928 pci_power_t state = platform_pci_choose_state(dev); in pci_target_state()
1936 if (pci_no_d1d2(dev)) in pci_target_state()
1941 } else if (!dev->pm_cap) { in pci_target_state()
1943 } else if (device_may_wakeup(&dev->dev)) { in pci_target_state()
1949 if (dev->pme_support) { in pci_target_state()
1951 && !(dev->pme_support & (1 << target_state))) in pci_target_state()
1967 int pci_prepare_to_sleep(struct pci_dev *dev) in pci_prepare_to_sleep() argument
1969 pci_power_t target_state = pci_target_state(dev); in pci_prepare_to_sleep()
1975 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); in pci_prepare_to_sleep()
1977 error = pci_set_power_state(dev, target_state); in pci_prepare_to_sleep()
1980 pci_enable_wake(dev, target_state, false); in pci_prepare_to_sleep()
1992 int pci_back_from_sleep(struct pci_dev *dev) in pci_back_from_sleep() argument
1994 pci_enable_wake(dev, PCI_D0, false); in pci_back_from_sleep()
1995 return pci_set_power_state(dev, PCI_D0); in pci_back_from_sleep()
2006 int pci_finish_runtime_suspend(struct pci_dev *dev) in pci_finish_runtime_suspend() argument
2008 pci_power_t target_state = pci_target_state(dev); in pci_finish_runtime_suspend()
2014 dev->runtime_d3cold = target_state == PCI_D3cold; in pci_finish_runtime_suspend()
2016 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); in pci_finish_runtime_suspend()
2018 error = pci_set_power_state(dev, target_state); in pci_finish_runtime_suspend()
2021 __pci_enable_wake(dev, target_state, true, false); in pci_finish_runtime_suspend()
2022 dev->runtime_d3cold = false; in pci_finish_runtime_suspend()
2036 bool pci_dev_run_wake(struct pci_dev *dev) in pci_dev_run_wake() argument
2038 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2040 if (device_run_wake(&dev->dev)) in pci_dev_run_wake()
2043 if (!dev->pme_support) in pci_dev_run_wake()
2049 if (device_run_wake(&bridge->dev)) in pci_dev_run_wake()
2077 struct device *dev = &pci_dev->dev; in pci_dev_keep_suspended() local
2079 if (!pm_runtime_suspended(dev) in pci_dev_keep_suspended()
2094 spin_lock_irq(&dev->power.lock); in pci_dev_keep_suspended()
2096 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && in pci_dev_keep_suspended()
2097 !device_may_wakeup(dev)) in pci_dev_keep_suspended()
2100 spin_unlock_irq(&dev->power.lock); in pci_dev_keep_suspended()
2114 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume() local
2119 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2121 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2124 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2129 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get() local
2130 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2134 pm_runtime_get_noresume(dev); in pci_config_pm_runtime_get()
2139 pm_runtime_barrier(dev); in pci_config_pm_runtime_get()
2146 pm_runtime_resume(dev); in pci_config_pm_runtime_get()
2151 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put() local
2152 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2154 pm_runtime_put(dev); in pci_config_pm_runtime_put()
2163 void pci_pm_init(struct pci_dev *dev) in pci_pm_init() argument
2168 pm_runtime_forbid(&dev->dev); in pci_pm_init()
2169 pm_runtime_set_active(&dev->dev); in pci_pm_init()
2170 pm_runtime_enable(&dev->dev); in pci_pm_init()
2171 device_enable_async_suspend(&dev->dev); in pci_pm_init()
2172 dev->wakeup_prepared = false; in pci_pm_init()
2174 dev->pm_cap = 0; in pci_pm_init()
2175 dev->pme_support = 0; in pci_pm_init()
2178 pm = pci_find_capability(dev, PCI_CAP_ID_PM); in pci_pm_init()
2182 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); in pci_pm_init()
2185 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", in pci_pm_init()
2190 dev->pm_cap = pm; in pci_pm_init()
2191 dev->d3_delay = PCI_PM_D3_WAIT; in pci_pm_init()
2192 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
2193 dev->d3cold_allowed = true; in pci_pm_init()
2195 dev->d1_support = false; in pci_pm_init()
2196 dev->d2_support = false; in pci_pm_init()
2197 if (!pci_no_d1d2(dev)) { in pci_pm_init()
2199 dev->d1_support = true; in pci_pm_init()
2201 dev->d2_support = true; in pci_pm_init()
2203 if (dev->d1_support || dev->d2_support) in pci_pm_init()
2204 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", in pci_pm_init()
2205 dev->d1_support ? " D1" : "", in pci_pm_init()
2206 dev->d2_support ? " D2" : ""); in pci_pm_init()
2211 dev_printk(KERN_DEBUG, &dev->dev, in pci_pm_init()
2218 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; in pci_pm_init()
2219 dev->pme_poll = true; in pci_pm_init()
2224 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
2226 pci_pme_active(dev, false); in pci_pm_init()
2230 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) in pci_ea_flags() argument
2253 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, in pci_ea_get_resource() argument
2257 return &dev->resource[bei]; in pci_ea_get_resource()
2261 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
2265 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
2271 static int pci_ea_read(struct pci_dev *dev, int offset) in pci_ea_read() argument
2281 pci_read_config_dword(dev, ent_offset, &dw0); in pci_ea_read()
2302 res = pci_ea_get_resource(dev, bei, prop); in pci_ea_read()
2304 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); in pci_ea_read()
2308 flags = pci_ea_flags(dev, prop); in pci_ea_read()
2310 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); in pci_ea_read()
2315 pci_read_config_dword(dev, ent_offset, &base); in pci_ea_read()
2320 pci_read_config_dword(dev, ent_offset, &max_offset); in pci_ea_read()
2327 pci_read_config_dword(dev, ent_offset, &base_upper); in pci_ea_read()
2346 pci_read_config_dword(dev, ent_offset, &max_offset_upper); in pci_ea_read()
2360 dev_err(&dev->dev, "EA Entry crosses address boundary\n"); in pci_ea_read()
2365 dev_err(&dev->dev, in pci_ea_read()
2371 res->name = pci_name(dev); in pci_ea_read()
2377 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", in pci_ea_read()
2380 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", in pci_ea_read()
2383 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", in pci_ea_read()
2386 …dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", in pci_ea_read()
2394 void pci_ea_init(struct pci_dev *dev) in pci_ea_init() argument
2402 ea = pci_find_capability(dev, PCI_CAP_ID_EA); in pci_ea_init()
2407 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
2414 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
2419 offset = pci_ea_read(dev, offset); in pci_ea_init()
2436 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, in _pci_add_cap_save_buffer() argument
2443 pos = pci_find_ext_capability(dev, cap); in _pci_add_cap_save_buffer()
2445 pos = pci_find_capability(dev, cap); in _pci_add_cap_save_buffer()
2457 pci_add_saved_cap(dev, save_state); in _pci_add_cap_save_buffer()
2462 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) in pci_add_cap_save_buffer() argument
2464 return _pci_add_cap_save_buffer(dev, cap, false, size); in pci_add_cap_save_buffer()
2467 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) in pci_add_ext_cap_save_buffer() argument
2469 return _pci_add_cap_save_buffer(dev, cap, true, size); in pci_add_ext_cap_save_buffer()
2476 void pci_allocate_cap_save_buffers(struct pci_dev *dev) in pci_allocate_cap_save_buffers() argument
2480 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, in pci_allocate_cap_save_buffers()
2483 dev_err(&dev->dev, in pci_allocate_cap_save_buffers()
2486 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); in pci_allocate_cap_save_buffers()
2488 dev_err(&dev->dev, in pci_allocate_cap_save_buffers()
2491 pci_allocate_vc_save_buffers(dev); in pci_allocate_cap_save_buffers()
2494 void pci_free_cap_save_buffers(struct pci_dev *dev) in pci_free_cap_save_buffers() argument
2499 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
2510 void pci_configure_ari(struct pci_dev *dev) in pci_configure_ari() argument
2515 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
2518 bridge = dev->bus->self; in pci_configure_ari()
2526 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { in pci_configure_ari()
2551 static int pci_std_enable_acs(struct pci_dev *dev) in pci_std_enable_acs() argument
2557 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_std_enable_acs()
2561 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); in pci_std_enable_acs()
2562 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); in pci_std_enable_acs()
2576 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); in pci_std_enable_acs()
2585 void pci_enable_acs(struct pci_dev *dev) in pci_enable_acs() argument
2590 if (!pci_std_enable_acs(dev)) in pci_enable_acs()
2593 pci_dev_specific_enable_acs(dev); in pci_enable_acs()
2737 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) in pci_swizzle_interrupt_pin() argument
2741 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
2744 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
2749 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) in pci_get_interrupt_pin() argument
2753 pin = dev->pin; in pci_get_interrupt_pin()
2757 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
2758 pin = pci_swizzle_interrupt_pin(dev, pin); in pci_get_interrupt_pin()
2759 dev = dev->bus->self; in pci_get_interrupt_pin()
2761 *bridge = dev; in pci_get_interrupt_pin()
2773 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) in pci_common_swizzle() argument
2777 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
2778 pin = pci_swizzle_interrupt_pin(dev, pin); in pci_common_swizzle()
2779 dev = dev->bus->self; in pci_common_swizzle()
2782 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
2859 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, in __pci_request_region()
3056 static void __pci_set_master(struct pci_dev *dev, bool enable) in __pci_set_master() argument
3060 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); in __pci_set_master()
3066 dev_dbg(&dev->dev, "%s bus mastering\n", in __pci_set_master()
3068 pci_write_config_word(dev, PCI_COMMAND, cmd); in __pci_set_master()
3070 dev->is_busmaster = enable; in __pci_set_master()
3093 void __weak pcibios_set_master(struct pci_dev *dev) in pcibios_set_master() argument
3098 if (pci_is_pcie(dev)) in pcibios_set_master()
3101 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); in pcibios_set_master()
3109 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); in pcibios_set_master()
3119 void pci_set_master(struct pci_dev *dev) in pci_set_master() argument
3121 __pci_set_master(dev, true); in pci_set_master()
3122 pcibios_set_master(dev); in pci_set_master()
3130 void pci_clear_master(struct pci_dev *dev) in pci_clear_master() argument
3132 __pci_set_master(dev, false); in pci_clear_master()
3146 int pci_set_cacheline_size(struct pci_dev *dev) in pci_set_cacheline_size() argument
3155 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
3161 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); in pci_set_cacheline_size()
3163 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
3167 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", in pci_set_cacheline_size()
3182 int pci_set_mwi(struct pci_dev *dev) in pci_set_mwi() argument
3190 rc = pci_set_cacheline_size(dev); in pci_set_mwi()
3194 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_set_mwi()
3196 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
3198 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_set_mwi()
3214 int pci_try_set_mwi(struct pci_dev *dev) in pci_try_set_mwi() argument
3219 return pci_set_mwi(dev); in pci_try_set_mwi()
3230 void pci_clear_mwi(struct pci_dev *dev) in pci_clear_mwi() argument
3235 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_clear_mwi()
3238 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_clear_mwi()
3283 bool pci_intx_mask_supported(struct pci_dev *dev) in pci_intx_mask_supported() argument
3288 if (dev->broken_intx_masking) in pci_intx_mask_supported()
3291 pci_cfg_access_lock(dev); in pci_intx_mask_supported()
3293 pci_read_config_word(dev, PCI_COMMAND, &orig); in pci_intx_mask_supported()
3294 pci_write_config_word(dev, PCI_COMMAND, in pci_intx_mask_supported()
3296 pci_read_config_word(dev, PCI_COMMAND, &new); in pci_intx_mask_supported()
3304 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", in pci_intx_mask_supported()
3308 pci_write_config_word(dev, PCI_COMMAND, orig); in pci_intx_mask_supported()
3311 pci_cfg_access_unlock(dev); in pci_intx_mask_supported()
3316 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) in pci_check_and_set_intx_mask() argument
3318 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
3334 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
3353 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
3369 bool pci_check_and_mask_intx(struct pci_dev *dev) in pci_check_and_mask_intx() argument
3371 return pci_check_and_set_intx_mask(dev, true); in pci_check_and_mask_intx()
3383 bool pci_check_and_unmask_intx(struct pci_dev *dev) in pci_check_and_unmask_intx() argument
3385 return pci_check_and_set_intx_mask(dev, false); in pci_check_and_unmask_intx()
3389 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) in pci_set_dma_max_seg_size() argument
3391 return dma_set_max_seg_size(&dev->dev, size); in pci_set_dma_max_seg_size()
3395 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) in pci_set_dma_seg_boundary() argument
3397 return dma_set_seg_boundary(&dev->dev, mask); in pci_set_dma_seg_boundary()
3407 int pci_wait_for_pending_transaction(struct pci_dev *dev) in pci_wait_for_pending_transaction() argument
3409 if (!pci_is_pcie(dev)) in pci_wait_for_pending_transaction()
3412 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, in pci_wait_for_pending_transaction()
3417 static int pcie_flr(struct pci_dev *dev, int probe) in pcie_flr() argument
3421 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); in pcie_flr()
3428 if (!pci_wait_for_pending_transaction(dev)) in pcie_flr()
3429 …dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset any… in pcie_flr()
3431 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); in pcie_flr()
3436 static int pci_af_flr(struct pci_dev *dev, int probe) in pci_af_flr() argument
3441 pos = pci_find_capability(dev, PCI_CAP_ID_AF); in pci_af_flr()
3445 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); in pci_af_flr()
3457 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, in pci_af_flr()
3459 …dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset … in pci_af_flr()
3461 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); in pci_af_flr()
3481 static int pci_pm_reset(struct pci_dev *dev, int probe) in pci_pm_reset() argument
3485 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
3488 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
3495 if (dev->current_state != PCI_D0) in pci_pm_reset()
3500 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
3501 pci_dev_d3_sleep(dev); in pci_pm_reset()
3505 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
3506 pci_dev_d3_sleep(dev); in pci_pm_reset()
3511 void pci_reset_secondary_bus(struct pci_dev *dev) in pci_reset_secondary_bus() argument
3515 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); in pci_reset_secondary_bus()
3517 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); in pci_reset_secondary_bus()
3525 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); in pci_reset_secondary_bus()
3537 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) in pcibios_reset_secondary_bus() argument
3539 pci_reset_secondary_bus(dev); in pcibios_reset_secondary_bus()
3549 void pci_reset_bridge_secondary_bus(struct pci_dev *dev) in pci_reset_bridge_secondary_bus() argument
3551 pcibios_reset_secondary_bus(dev); in pci_reset_bridge_secondary_bus()
3555 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) in pci_parent_bus_reset() argument
3559 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
3560 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
3563 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
3564 if (pdev != dev) in pci_parent_bus_reset()
3570 pci_reset_bridge_secondary_bus(dev->bus->self); in pci_parent_bus_reset()
3590 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) in pci_dev_reset_slot_function() argument
3594 if (dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
3595 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
3598 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_dev_reset_slot_function()
3599 if (pdev != dev && pdev->slot == dev->slot) in pci_dev_reset_slot_function()
3602 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
3605 static int __pci_dev_reset(struct pci_dev *dev, int probe) in __pci_dev_reset() argument
3611 rc = pci_dev_specific_reset(dev, probe); in __pci_dev_reset()
3615 rc = pcie_flr(dev, probe); in __pci_dev_reset()
3619 rc = pci_af_flr(dev, probe); in __pci_dev_reset()
3623 rc = pci_pm_reset(dev, probe); in __pci_dev_reset()
3627 rc = pci_dev_reset_slot_function(dev, probe); in __pci_dev_reset()
3631 rc = pci_parent_bus_reset(dev, probe); in __pci_dev_reset()
3636 static void pci_dev_lock(struct pci_dev *dev) in pci_dev_lock() argument
3638 pci_cfg_access_lock(dev); in pci_dev_lock()
3640 device_lock(&dev->dev); in pci_dev_lock()
3644 static int pci_dev_trylock(struct pci_dev *dev) in pci_dev_trylock() argument
3646 if (pci_cfg_access_trylock(dev)) { in pci_dev_trylock()
3647 if (device_trylock(&dev->dev)) in pci_dev_trylock()
3649 pci_cfg_access_unlock(dev); in pci_dev_trylock()
3655 static void pci_dev_unlock(struct pci_dev *dev) in pci_dev_unlock() argument
3657 device_unlock(&dev->dev); in pci_dev_unlock()
3658 pci_cfg_access_unlock(dev); in pci_dev_unlock()
3670 static void pci_reset_notify(struct pci_dev *dev, bool prepare) in pci_reset_notify() argument
3673 dev->driver ? dev->driver->err_handler : NULL; in pci_reset_notify()
3675 err_handler->reset_notify(dev, prepare); in pci_reset_notify()
3678 static void pci_dev_save_and_disable(struct pci_dev *dev) in pci_dev_save_and_disable() argument
3680 pci_reset_notify(dev, true); in pci_dev_save_and_disable()
3687 pci_set_power_state(dev, PCI_D0); in pci_dev_save_and_disable()
3689 pci_save_state(dev); in pci_dev_save_and_disable()
3697 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); in pci_dev_save_and_disable()
3700 static void pci_dev_restore(struct pci_dev *dev) in pci_dev_restore() argument
3702 pci_restore_state(dev); in pci_dev_restore()
3703 pci_reset_notify(dev, false); in pci_dev_restore()
3706 static int pci_dev_reset(struct pci_dev *dev, int probe) in pci_dev_reset() argument
3711 pci_dev_lock(dev); in pci_dev_reset()
3713 rc = __pci_dev_reset(dev, probe); in pci_dev_reset()
3716 pci_dev_unlock(dev); in pci_dev_reset()
3738 int __pci_reset_function(struct pci_dev *dev) in __pci_reset_function() argument
3740 return pci_dev_reset(dev, 0); in __pci_reset_function()
3763 int __pci_reset_function_locked(struct pci_dev *dev) in __pci_reset_function_locked() argument
3765 return __pci_dev_reset(dev, 0); in __pci_reset_function_locked()
3780 int pci_probe_reset_function(struct pci_dev *dev) in pci_probe_reset_function() argument
3782 return pci_dev_reset(dev, 1); in pci_probe_reset_function()
3801 int pci_reset_function(struct pci_dev *dev) in pci_reset_function() argument
3805 rc = pci_dev_reset(dev, 1); in pci_reset_function()
3809 pci_dev_save_and_disable(dev); in pci_reset_function()
3811 rc = pci_dev_reset(dev, 0); in pci_reset_function()
3813 pci_dev_restore(dev); in pci_reset_function()
3825 int pci_try_reset_function(struct pci_dev *dev) in pci_try_reset_function() argument
3829 rc = pci_dev_reset(dev, 1); in pci_try_reset_function()
3833 pci_dev_save_and_disable(dev); in pci_try_reset_function()
3835 if (pci_dev_trylock(dev)) { in pci_try_reset_function()
3836 rc = __pci_dev_reset(dev, 0); in pci_try_reset_function()
3837 pci_dev_unlock(dev); in pci_try_reset_function()
3841 pci_dev_restore(dev); in pci_try_reset_function()
3850 struct pci_dev *dev; in pci_bus_resetable() local
3852 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resetable()
3853 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resetable()
3854 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_bus_resetable()
3864 struct pci_dev *dev; in pci_bus_lock() local
3866 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
3867 pci_dev_lock(dev); in pci_bus_lock()
3868 if (dev->subordinate) in pci_bus_lock()
3869 pci_bus_lock(dev->subordinate); in pci_bus_lock()
3876 struct pci_dev *dev; in pci_bus_unlock() local
3878 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
3879 if (dev->subordinate) in pci_bus_unlock()
3880 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
3881 pci_dev_unlock(dev); in pci_bus_unlock()
3888 struct pci_dev *dev; in pci_bus_trylock() local
3890 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
3891 if (!pci_dev_trylock(dev)) in pci_bus_trylock()
3893 if (dev->subordinate) { in pci_bus_trylock()
3894 if (!pci_bus_trylock(dev->subordinate)) { in pci_bus_trylock()
3895 pci_dev_unlock(dev); in pci_bus_trylock()
3903 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
3904 if (dev->subordinate) in pci_bus_trylock()
3905 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
3906 pci_dev_unlock(dev); in pci_bus_trylock()
3914 struct pci_dev *dev; in pci_slot_resetable() local
3916 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resetable()
3917 if (!dev->slot || dev->slot != slot) in pci_slot_resetable()
3919 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resetable()
3920 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_slot_resetable()
3930 struct pci_dev *dev; in pci_slot_lock() local
3932 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
3933 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
3935 pci_dev_lock(dev); in pci_slot_lock()
3936 if (dev->subordinate) in pci_slot_lock()
3937 pci_bus_lock(dev->subordinate); in pci_slot_lock()
3944 struct pci_dev *dev; in pci_slot_unlock() local
3946 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
3947 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
3949 if (dev->subordinate) in pci_slot_unlock()
3950 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
3951 pci_dev_unlock(dev); in pci_slot_unlock()
3958 struct pci_dev *dev; in pci_slot_trylock() local
3960 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
3961 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
3963 if (!pci_dev_trylock(dev)) in pci_slot_trylock()
3965 if (dev->subordinate) { in pci_slot_trylock()
3966 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
3967 pci_dev_unlock(dev); in pci_slot_trylock()
3975 list_for_each_entry_continue_reverse(dev, in pci_slot_trylock()
3977 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
3979 if (dev->subordinate) in pci_slot_trylock()
3980 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
3981 pci_dev_unlock(dev); in pci_slot_trylock()
3989 struct pci_dev *dev; in pci_bus_save_and_disable() local
3991 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable()
3992 pci_dev_save_and_disable(dev); in pci_bus_save_and_disable()
3993 if (dev->subordinate) in pci_bus_save_and_disable()
3994 pci_bus_save_and_disable(dev->subordinate); in pci_bus_save_and_disable()
4004 struct pci_dev *dev; in pci_bus_restore() local
4006 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore()
4007 pci_dev_restore(dev); in pci_bus_restore()
4008 if (dev->subordinate) in pci_bus_restore()
4009 pci_bus_restore(dev->subordinate); in pci_bus_restore()
4016 struct pci_dev *dev; in pci_slot_save_and_disable() local
4018 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable()
4019 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable()
4021 pci_dev_save_and_disable(dev); in pci_slot_save_and_disable()
4022 if (dev->subordinate) in pci_slot_save_and_disable()
4023 pci_bus_save_and_disable(dev->subordinate); in pci_slot_save_and_disable()
4033 struct pci_dev *dev; in pci_slot_restore() local
4035 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore()
4036 if (!dev->slot || dev->slot != slot) in pci_slot_restore()
4038 pci_dev_restore(dev); in pci_slot_restore()
4039 if (dev->subordinate) in pci_slot_restore()
4040 pci_bus_restore(dev->subordinate); in pci_slot_restore()
4232 int pcix_get_max_mmrbc(struct pci_dev *dev) in pcix_get_max_mmrbc() argument
4237 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pcix_get_max_mmrbc()
4241 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) in pcix_get_max_mmrbc()
4255 int pcix_get_mmrbc(struct pci_dev *dev) in pcix_get_mmrbc() argument
4260 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pcix_get_mmrbc()
4264 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) in pcix_get_mmrbc()
4280 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) in pcix_set_mmrbc() argument
4291 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pcix_set_mmrbc()
4295 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) in pcix_set_mmrbc()
4301 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) in pcix_set_mmrbc()
4306 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
4311 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) in pcix_set_mmrbc()
4325 int pcie_get_readrq(struct pci_dev *dev) in pcie_get_readrq() argument
4329 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); in pcie_get_readrq()
4343 int pcie_set_readrq(struct pci_dev *dev, int rq) in pcie_set_readrq() argument
4357 int mps = pcie_get_mps(dev); in pcie_set_readrq()
4365 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, in pcie_set_readrq()
4376 int pcie_get_mps(struct pci_dev *dev) in pcie_get_mps() argument
4380 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); in pcie_get_mps()
4394 int pcie_set_mps(struct pci_dev *dev, int mps) in pcie_set_mps() argument
4402 if (v > dev->pcie_mpss) in pcie_set_mps()
4406 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, in pcie_set_mps()
4420 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, in pcie_get_minimum_link() argument
4428 while (dev) { in pcie_get_minimum_link()
4433 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); in pcie_get_minimum_link()
4447 dev = dev->bus->self; in pcie_get_minimum_link()
4461 int pci_select_bars(struct pci_dev *dev, unsigned long flags) in pci_select_bars() argument
4465 if (pci_resource_flags(dev, i) & flags) in pci_select_bars()
4479 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) in pci_resource_bar() argument
4488 return dev->rom_base_reg; in pci_resource_bar()
4492 reg = pci_iov_resource_bar(dev, resno); in pci_resource_bar()
4497 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); in pci_resource_bar()
4509 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, in pci_set_vga_state_arch() argument
4513 return arch_set_vga_state(dev, decode, command_bits, in pci_set_vga_state_arch()
4526 int pci_set_vga_state(struct pci_dev *dev, bool decode, in pci_set_vga_state() argument
4537 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); in pci_set_vga_state()
4542 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_set_vga_state()
4547 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_set_vga_state()
4553 bus = dev->bus; in pci_set_vga_state()
4579 void pci_ignore_hotplug(struct pci_dev *dev) in pci_ignore_hotplug() argument
4581 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
4583 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
4601 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) in pci_specified_resource_alignment() argument
4629 if (seg == pci_domain_nr(dev->bus) && in pci_specified_resource_alignment()
4630 bus == dev->bus->number && in pci_specified_resource_alignment()
4631 slot == PCI_SLOT(dev->devfn) && in pci_specified_resource_alignment()
4632 func == PCI_FUNC(dev->devfn)) { in pci_specified_resource_alignment()
4657 void pci_reassigndev_resource_alignment(struct pci_dev *dev) in pci_reassigndev_resource_alignment() argument
4665 align = pci_specified_resource_alignment(dev); in pci_reassigndev_resource_alignment()
4669 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
4670 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
4671 dev_warn(&dev->dev, in pci_reassigndev_resource_alignment()
4676 dev_info(&dev->dev, in pci_reassigndev_resource_alignment()
4678 pci_read_config_word(dev, PCI_COMMAND, &command); in pci_reassigndev_resource_alignment()
4680 pci_write_config_word(dev, PCI_COMMAND, command); in pci_reassigndev_resource_alignment()
4683 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
4689 dev_info(&dev->dev, in pci_reassigndev_resource_alignment()
4701 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in pci_reassigndev_resource_alignment()
4702 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in pci_reassigndev_resource_alignment()
4704 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
4711 pci_disable_bridge_window(dev); in pci_reassigndev_resource_alignment()