49 	u32 revision = fields[1].integer.value;  in decode_type0_hpx_record()
60 		hpx->t0->cache_line_size = fields[2].integer.value;  in decode_type0_hpx_record()
61 		hpx->t0->latency_timer   = fields[3].integer.value;  in decode_type0_hpx_record()
62 		hpx->t0->enable_serr     = fields[4].integer.value;  in decode_type0_hpx_record()
63 		hpx->t0->enable_perr     = fields[5].integer.value;  in decode_type0_hpx_record()
79 	u32 revision = fields[1].integer.value;  in decode_type1_hpx_record()
90 		hpx->t1->max_mem_read  = fields[2].integer.value;  in decode_type1_hpx_record()
91 		hpx->t1->avg_max_split = fields[3].integer.value;  in decode_type1_hpx_record()
92 		hpx->t1->tot_max_split = fields[4].integer.value;  in decode_type1_hpx_record()
108 	u32 revision = fields[1].integer.value;  in decode_type2_hpx_record()
119 		hpx->t2->unc_err_mask_and      = fields[2].integer.value;  in decode_type2_hpx_record()
120 		hpx->t2->unc_err_mask_or       = fields[3].integer.value;  in decode_type2_hpx_record()
121 		hpx->t2->unc_err_sever_and     = fields[4].integer.value;  in decode_type2_hpx_record()
122 		hpx->t2->unc_err_sever_or      = fields[5].integer.value;  in decode_type2_hpx_record()
123 		hpx->t2->cor_err_mask_and      = fields[6].integer.value;  in decode_type2_hpx_record()
124 		hpx->t2->cor_err_mask_or       = fields[7].integer.value;  in decode_type2_hpx_record()
125 		hpx->t2->adv_err_cap_and       = fields[8].integer.value;  in decode_type2_hpx_record()
126 		hpx->t2->adv_err_cap_or        = fields[9].integer.value;  in decode_type2_hpx_record()
127 		hpx->t2->pci_exp_devctl_and    = fields[10].integer.value;  in decode_type2_hpx_record()
128 		hpx->t2->pci_exp_devctl_or     = fields[11].integer.value;  in decode_type2_hpx_record()
129 		hpx->t2->pci_exp_lnkctl_and    = fields[12].integer.value;  in decode_type2_hpx_record()
130 		hpx->t2->pci_exp_lnkctl_or     = fields[13].integer.value;  in decode_type2_hpx_record()
131 		hpx->t2->sec_unc_err_sever_and = fields[14].integer.value;  in decode_type2_hpx_record()
132 		hpx->t2->sec_unc_err_sever_or  = fields[15].integer.value;  in decode_type2_hpx_record()
133 		hpx->t2->sec_unc_err_mask_and  = fields[16].integer.value;  in decode_type2_hpx_record()
134 		hpx->t2->sec_unc_err_mask_or   = fields[17].integer.value;  in decode_type2_hpx_record()
180 		type = fields[0].integer.value;  in acpi_run_hpx()
239 	hpp->t0->cache_line_size = fields[0].integer.value;  in acpi_run_hpp()
240 	hpp->t0->latency_timer   = fields[1].integer.value;  in acpi_run_hpp()
241 	hpp->t0->enable_serr     = fields[2].integer.value;  in acpi_run_hpp()
242 	hpp->t0->enable_perr     = fields[3].integer.value;  in acpi_run_hpp()
564 	if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {  in acpi_pci_add_bus()
618 	int value;  in pci_acpi_optimize_delay()  local
632 			value = (int)elements[0].integer.value / 1000;  in pci_acpi_optimize_delay()
633 			if (value < PCI_PM_D3COLD_WAIT)  in pci_acpi_optimize_delay()
634 				pdev->d3cold_delay = value;  in pci_acpi_optimize_delay()
637 			value = (int)elements[3].integer.value / 1000;  in pci_acpi_optimize_delay()
638 			if (value < PCI_PM_D3_WAIT)  in pci_acpi_optimize_delay()
639 				pdev->d3_delay = value;  in pci_acpi_optimize_delay()