148 	struct mvebu_sw_pci_bridge bridge;  member
385 	if (port->bridge.iolimit < port->bridge.iobase ||  in mvebu_pcie_handle_iobase_change()
386 	    port->bridge.iolimitupper < port->bridge.iobaseupper ||  in mvebu_pcie_handle_iobase_change()
387 	    !(port->bridge.command & PCI_COMMAND_IO)) {  in mvebu_pcie_handle_iobase_change()
413 	iobase = ((port->bridge.iobase & 0xF0) << 8) |  in mvebu_pcie_handle_iobase_change()
414 		(port->bridge.iobaseupper << 16);  in mvebu_pcie_handle_iobase_change()
416 	port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |  in mvebu_pcie_handle_iobase_change()
417 			    (port->bridge.iolimitupper << 16)) -  in mvebu_pcie_handle_iobase_change()
428 	if (port->bridge.memlimit < port->bridge.membase ||  in mvebu_pcie_handle_membase_change()
429 	    !(port->bridge.command & PCI_COMMAND_MEMORY)) {  in mvebu_pcie_handle_membase_change()
448 	port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);  in mvebu_pcie_handle_membase_change()
450 		(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -  in mvebu_pcie_handle_membase_change()
464 	struct mvebu_sw_pci_bridge *bridge = &port->bridge;  in mvebu_sw_pci_bridge_init()  local
466 	memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));  in mvebu_sw_pci_bridge_init()
468 	bridge->class = PCI_CLASS_BRIDGE_PCI;  in mvebu_sw_pci_bridge_init()
469 	bridge->vendor = PCI_VENDOR_ID_MARVELL;  in mvebu_sw_pci_bridge_init()
470 	bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;  in mvebu_sw_pci_bridge_init()
471 	bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;  in mvebu_sw_pci_bridge_init()
472 	bridge->header_type = PCI_HEADER_TYPE_BRIDGE;  in mvebu_sw_pci_bridge_init()
473 	bridge->cache_line_size = 0x10;  in mvebu_sw_pci_bridge_init()
476 	bridge->iobase = PCI_IO_RANGE_TYPE_32;  in mvebu_sw_pci_bridge_init()
477 	bridge->iolimit = PCI_IO_RANGE_TYPE_32;  in mvebu_sw_pci_bridge_init()
480 	bridge->status = PCI_STATUS_CAP_LIST;  in mvebu_sw_pci_bridge_init()
490 	struct mvebu_sw_pci_bridge *bridge = &port->bridge;  in mvebu_sw_pci_bridge_read()  local
494 		*value = bridge->device << 16 | bridge->vendor;  in mvebu_sw_pci_bridge_read()
498 		*value = bridge->command | bridge->status << 16;  in mvebu_sw_pci_bridge_read()
502 		*value = bridge->class << 16 | bridge->interface << 8 |  in mvebu_sw_pci_bridge_read()
503 			 bridge->revision;  in mvebu_sw_pci_bridge_read()
507 		*value = bridge->bist << 24 | bridge->header_type << 16 |  in mvebu_sw_pci_bridge_read()
508 			 bridge->latency_timer << 8 | bridge->cache_line_size;  in mvebu_sw_pci_bridge_read()
512 		*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];  in mvebu_sw_pci_bridge_read()
516 		*value = (bridge->secondary_latency_timer << 24 |  in mvebu_sw_pci_bridge_read()
517 			  bridge->subordinate_bus         << 16 |  in mvebu_sw_pci_bridge_read()
518 			  bridge->secondary_bus           <<  8 |  in mvebu_sw_pci_bridge_read()
519 			  bridge->primary_bus);  in mvebu_sw_pci_bridge_read()
524 			*value = bridge->secondary_status << 16;  in mvebu_sw_pci_bridge_read()
526 			*value = (bridge->secondary_status << 16 |  in mvebu_sw_pci_bridge_read()
527 				  bridge->iolimit          <<  8 |  in mvebu_sw_pci_bridge_read()
528 				  bridge->iobase);  in mvebu_sw_pci_bridge_read()
532 		*value = (bridge->memlimit << 16 | bridge->membase);  in mvebu_sw_pci_bridge_read()
540 		*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);  in mvebu_sw_pci_bridge_read()
570 		*value |= bridge->pcie_devctl;  in mvebu_sw_pci_bridge_read()
587 		*value = bridge->pcie_sltcap;  in mvebu_sw_pci_bridge_read()
595 		*value = bridge->pcie_rtctl;  in mvebu_sw_pci_bridge_read()
631 	struct mvebu_sw_pci_bridge *bridge = &port->bridge;  in mvebu_sw_pci_bridge_write()  local
653 		u32 old = bridge->command;  in mvebu_sw_pci_bridge_write()
658 		bridge->command = value & 0xffff;  in mvebu_sw_pci_bridge_write()
659 		if ((old ^ bridge->command) & PCI_COMMAND_IO)  in mvebu_sw_pci_bridge_write()
661 		if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)  in mvebu_sw_pci_bridge_write()
667 		bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;  in mvebu_sw_pci_bridge_write()
676 		bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;  in mvebu_sw_pci_bridge_write()
677 		bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;  in mvebu_sw_pci_bridge_write()
682 		bridge->membase = value & 0xffff;  in mvebu_sw_pci_bridge_write()
683 		bridge->memlimit = value >> 16;  in mvebu_sw_pci_bridge_write()
688 		bridge->iobaseupper = value & 0xffff;  in mvebu_sw_pci_bridge_write()
689 		bridge->iolimitupper = value >> 16;  in mvebu_sw_pci_bridge_write()
694 		bridge->primary_bus             = value & 0xff;  in mvebu_sw_pci_bridge_write()
695 		bridge->secondary_bus           = (value >> 8) & 0xff;  in mvebu_sw_pci_bridge_write()
696 		bridge->subordinate_bus         = (value >> 16) & 0xff;  in mvebu_sw_pci_bridge_write()
697 		bridge->secondary_latency_timer = (value >> 24) & 0xff;  in mvebu_sw_pci_bridge_write()
698 		mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);  in mvebu_sw_pci_bridge_write()
770 		    bus->number >= port->bridge.secondary_bus &&  in mvebu_pcie_find_port()
771 		    bus->number <= port->bridge.subordinate_bus)  in mvebu_pcie_find_port()