110 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)  argument
114 #define LBA_DEV(d) ((struct lba_device *) (d))  argument
160 lba_dump_res(struct resource *r, int d)  in lba_dump_res()  argument
168 	for (i = d; i ; --i) printk(" ");  in lba_dump_res()
171 	lba_dump_res(r->child, d+2);  in lba_dump_res()
172 	lba_dump_res(r->sibling, d);  in lba_dump_res()
190 static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)  in lba_device_present()  argument
192 	u8 first_bus = d->hba.hba_bus->busn_res.start;  in lba_device_present()
193 	u8 last_sub_bus = d->hba.hba_bus->busn_res.end;  in lba_device_present()
206 #define LBA_CFG_SETUP(d, tok) {				\  argument
208     error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);		\
211     status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);		\
217 	arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);		\
223 	WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK);		\
229     WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG);	\
233 #define LBA_CFG_PROBE(d, tok) {				\  argument
238     WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
243     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
248     WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA);		\
253     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
284 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) {		\  argument
307 #define LBA_CFG_TR4_ADDR_SETUP(d, addr)					\  argument
308 	WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
310 #define LBA_CFG_ADDR_SETUP(d, addr) {					\  argument
311     WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
316     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
320 #define LBA_CFG_RESTORE(d, base) {					\  argument
338 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)  in lba_rd_cfg()  argument
346 	LBA_CFG_SETUP(d, tok);  in lba_rd_cfg()
347 	LBA_CFG_PROBE(d, tok);  in lba_rd_cfg()
348 	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);  in lba_rd_cfg()
350 		void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;  in lba_rd_cfg()
352 		LBA_CFG_ADDR_SETUP(d, tok | reg);  in lba_rd_cfg()
359 	LBA_CFG_RESTORE(d, d->hba.base_addr);  in lba_rd_cfg()
366 	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));  in elroy_cfg_read()  local
369 	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;  in elroy_cfg_read()
378 		*data = lba_rd_cfg(d, tok, pos, size);  in elroy_cfg_read()
383 	if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {  in elroy_cfg_read()
394 	LBA_CFG_ADDR_SETUP(d, tok | pos);  in elroy_cfg_read()
406 lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)  in lba_wr_cfg()  argument
412 	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;  in lba_wr_cfg()
414 	LBA_CFG_SETUP(d, tok);  in lba_wr_cfg()
415 	LBA_CFG_ADDR_SETUP(d, tok | reg);  in lba_wr_cfg()
421 	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);  in lba_wr_cfg()
422 	LBA_CFG_RESTORE(d, d->hba.base_addr);  in lba_wr_cfg()
433 	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));  in elroy_cfg_write()  local
440 	if (!LBA_SKIP_PROBE(d)) {  in elroy_cfg_write()
442 		lba_wr_cfg(d, tok, pos, (u32) data, size);  in elroy_cfg_write()
447 	if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {  in elroy_cfg_write()
455 	LBA_CFG_ADDR_SETUP(d, tok | pos);  in elroy_cfg_write()
457 	case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));  in elroy_cfg_write()
459 	case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));  in elroy_cfg_write()
461 	case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);  in elroy_cfg_write()
465 	lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);  in elroy_cfg_write()
483 	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));  in mercury_cfg_read()  local
486 	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;  in mercury_cfg_read()
491 	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);  in mercury_cfg_read()
515 	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));  in mercury_cfg_write()  local
516 	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;  in mercury_cfg_write()
525 	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);  in mercury_cfg_write()
539 	lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);  in mercury_cfg_write()
851 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
892 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
894 	DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
896 	if (LBA_DEV(d)->hw_rev < 3) \
897 		lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
1318 lba_hw_init(struct lba_device *d)  in lba_hw_init()  argument
1325 		d->hba.base_addr,  in lba_hw_init()
1326 		READ_REG64(d->hba.base_addr + LBA_STAT_CTL),  in lba_hw_init()
1327 		READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),  in lba_hw_init()
1328 		READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),  in lba_hw_init()
1329 		READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );  in lba_hw_init()
1331 		READ_REG64(d->hba.base_addr + LBA_ARB_MASK),  in lba_hw_init()
1332 		READ_REG64(d->hba.base_addr + LBA_ARB_PRI),  in lba_hw_init()
1333 		READ_REG64(d->hba.base_addr + LBA_ARB_MODE),  in lba_hw_init()
1334 		READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );  in lba_hw_init()
1336 		READ_REG64(d->hba.base_addr + LBA_HINT_CFG));  in lba_hw_init()
1340 		printk(" %Lx", READ_REG64(d->hba.base_addr + i));  in lba_hw_init()
1354 	bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;  in lba_hw_init()
1359 	stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);  in lba_hw_init()
1363 		WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);  in lba_hw_init()
1367         stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);  in lba_hw_init()
1368 	WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);  in lba_hw_init()
1378 	if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {  in lba_hw_init()
1389 		WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);  in lba_hw_init()