1207 static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)  in atom_ppd_topo()  argument
1209 	switch (ppd & ATOM_PPD_TOPO_MASK) {  in atom_ppd_topo()
1211 		dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd);  in atom_ppd_topo()
1215 		dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd);  in atom_ppd_topo()
1222 		dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd);  in atom_ppd_topo()
1226 	dev_dbg(ndev_dev(ndev), "PPD %d invalid\n", ppd);  in atom_ppd_topo()
1359 	u32 ppd;  in atom_init_dev()  local
1362 	rc = pci_read_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, &ppd);  in atom_init_dev()
1366 	ndev->ntb.topo = atom_ppd_topo(ndev, ppd);  in atom_init_dev()
1381 					    ppd | ATOM_PPD_INIT_LINK);  in atom_init_dev()
1436 static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)  in xeon_ppd_topo()  argument
1438 	switch (ppd & XEON_PPD_TOPO_MASK) {  in xeon_ppd_topo()
1457 static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd)  in xeon_ppd_bar4_split()  argument
1459 	if (ppd & XEON_PPD_SPLIT_BAR_MASK) {  in xeon_ppd_bar4_split()
1460 		dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd);  in xeon_ppd_bar4_split()
1835 	u8 ppd;  in xeon_init_dev()  local
1909 	rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);  in xeon_init_dev()
1913 	ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);  in xeon_init_dev()
1914 	dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,  in xeon_init_dev()
1920 		ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd);  in xeon_init_dev()
1922 			ppd, ndev->bar4_split);  in xeon_init_dev()