Lines Matching refs:iowrite64
164 #ifndef iowrite64
166 #define iowrite64 writeq macro
168 #define iowrite64 _iowrite64 macro
887 iowrite64(addr, mmio + xlat_reg); in intel_ntb_mw_set_trans()
890 iowrite64(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
895 iowrite64(limit, mmio + limit_reg); in intel_ntb_mw_set_trans()
898 iowrite64(base, mmio + limit_reg); in intel_ntb_mw_set_trans()
899 iowrite64(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
1170 iowrite64(bits, mmio); in atom_db_iowrite()
1595 iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET); in xeon_setup_b2b_mw()
1603 iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET); in xeon_setup_b2b_mw()
1610 iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET); in xeon_setup_b2b_mw()
1630 iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET); in xeon_setup_b2b_mw()
1637 iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET); in xeon_setup_b2b_mw()
1655 iowrite64(0, mmio + XEON_SBAR23XLAT_OFFSET); in xeon_setup_b2b_mw()
1658 iowrite64(0, mmio + XEON_SBAR45XLAT_OFFSET); in xeon_setup_b2b_mw()
1665 iowrite64(0, mmio + XEON_PBAR23LMT_OFFSET); in xeon_setup_b2b_mw()
1667 iowrite64(0, mmio + XEON_PBAR45LMT_OFFSET); in xeon_setup_b2b_mw()
1675 iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET); in xeon_setup_b2b_mw()
1681 iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET); in xeon_setup_b2b_mw()