148 #ifndef ioread64
150 #define ioread64 readq  macro
152 #define ioread64 _ioread64  macro
637 	u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2));  in ndev_debugfs_read()
650 		u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4));  in ndev_debugfs_read()
655 	u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2));  in ndev_debugfs_read()
667 		u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4));  in ndev_debugfs_read()
677 			u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);  in ndev_debugfs_read()
691 				u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);  in ndev_debugfs_read()
697 			u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET);  in ndev_debugfs_read()
711 				u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET);  in ndev_debugfs_read()
720 			u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET);  in ndev_debugfs_read()
724 			u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET);  in ndev_debugfs_read()
736 				u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET);  in ndev_debugfs_read()
878 		base = ioread64(mmio + base_reg);  in intel_ntb_mw_set_trans()
888 		reg_val = ioread64(mmio + xlat_reg);  in intel_ntb_mw_set_trans()
896 		reg_val = ioread64(mmio + limit_reg);  in intel_ntb_mw_set_trans()
1165 	return ioread64(mmio);  in atom_db_ioread()
1604 	bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);  in xeon_setup_b2b_mw()
1611 		bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);  in xeon_setup_b2b_mw()
1631 	bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);  in xeon_setup_b2b_mw()
1638 		bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);  in xeon_setup_b2b_mw()
1676 	bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);  in xeon_setup_b2b_mw()
1682 		bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);  in xeon_setup_b2b_mw()