157 	low = ioread32(mmio);  in _ioread64()
158 	high = ioread32(mmio + sizeof(u32));  in _ioread64()
370 	return ioread32(mmio + (idx << 2));  in ndev_spad_read()
642 		u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4));  in ndev_debugfs_read()
646 		u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 5));  in ndev_debugfs_read()
660 		u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4));  in ndev_debugfs_read()
663 		u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 5));  in ndev_debugfs_read()
682 				u.v32 = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);  in ndev_debugfs_read()
686 				u.v32 = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);  in ndev_debugfs_read()
702 				u.v32 = ioread32(mmio + XEON_PBAR4LMT_OFFSET);  in ndev_debugfs_read()
706 				u.v32 = ioread32(mmio + XEON_PBAR5LMT_OFFSET);  in ndev_debugfs_read()
729 				u.v32 = ioread32(mmio + XEON_SBAR4BASE_OFFSET);  in ndev_debugfs_read()
732 				u.v32 = ioread32(mmio + XEON_SBAR5BASE_OFFSET);  in ndev_debugfs_read()
909 		base = ioread32(mmio + base_reg);  in intel_ntb_mw_set_trans()
919 		reg_val = ioread32(mmio + xlat_reg);  in intel_ntb_mw_set_trans()
927 		reg_val = ioread32(mmio + limit_reg);  in intel_ntb_mw_set_trans()
981 	ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);  in intel_ntb_link_enable()
1005 	ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);  in intel_ntb_link_disable()
1177 	ntb_ctl = ioread32(ndev->self_mmio + ATOM_NTBCNTL_OFFSET);  in atom_poll_link()
1184 	ndev->lnk_sta = ioread32(ndev->self_mmio + ATOM_LINK_STATUS_OFFSET);  in atom_poll_link()
1196 	if (ioread32(ndev->self_mmio + ATOM_LTSSMSTATEJMP_OFFSET)  in atom_link_is_err()
1200 	if (ioread32(ndev->self_mmio + ATOM_IBSTERRRCRVSTS0_OFFSET)  in atom_link_is_err()
1269 	status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);  in atom_link_hb()
1275 	status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);  in atom_link_hb()
1281 	status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);  in atom_link_hb()
1286 	status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);  in atom_link_hb()
1292 	status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);  in atom_link_hb()
1617 		bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET);  in xeon_setup_b2b_mw()
1623 		bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET);  in xeon_setup_b2b_mw()
1644 		bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET);  in xeon_setup_b2b_mw()
1650 		bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET);  in xeon_setup_b2b_mw()
1687 		bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);  in xeon_setup_b2b_mw()
1692 		bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);  in xeon_setup_b2b_mw()
1748 		ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);  in xeon_init_ntb()