Lines Matching refs:u8
39 u8 phy_standalone;
40 u8 spare0;
41 u8 enable_clpc;
42 u8 enable_tx_low_pwr_on_siso_rdl;
43 u8 auto_detect;
44 u8 dedicated_fem;
46 u8 low_band_component;
49 u8 low_band_component_type;
51 u8 high_band_component;
54 u8 high_band_component_type;
55 u8 number_of_assembled_ant2_4;
56 u8 number_of_assembled_ant5;
57 u8 pin_muxing_platform_options[PIN_MUXING_SIZE];
58 u8 external_pa_dc2dc;
59 u8 tcxo_ldo_voltage;
60 u8 xtal_itrim_val;
61 u8 srf_state;
62 u8 srf1[SRF_TABLE_LEN];
63 u8 srf2[SRF_TABLE_LEN];
64 u8 srf3[SRF_TABLE_LEN];
65 u8 io_configuration;
66 u8 sdio_configuration;
67 u8 settings;
68 u8 rx_profile;
69 u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG];
70 u8 pwr_limit_reference_11_abg;
71 u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P];
72 u8 pwr_limit_reference_11p;
73 u8 spare1;
74 u8 per_chan_bo_mode_11_abg[13];
75 u8 per_chan_bo_mode_11_p[4];
76 u8 primary_clock_setting_time;
77 u8 clock_valid_on_wake_up;
78 u8 secondary_clock_setting_time;
79 u8 board_type;
81 u8 psat;
88 u8 tx_rf_margin;
94 u8 padding[1];
110 u8 mode;
117 u8 idle_duty_cycle;
121 u8 connected_duty_cycle;
125 u8 max_stations_thresh;
129 u8 idle_conn_thresh;