74 	u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;  in wl1251_boot_init_seq()  local
117 	tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;  in wl1251_boot_init_seq()
118 	wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);  in wl1251_boot_init_seq()
136 		tmp = init_data - 0x21;  in wl1251_boot_init_seq()
138 		tmp = 0;  in wl1251_boot_init_seq()
139 	wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);  in wl1251_boot_init_seq()
157 	tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;  in wl1251_boot_init_seq()
158 	wl1251_reg_write32(wl, 0x00305840, tmp);  in wl1251_boot_init_seq()
163 	tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];  in wl1251_boot_init_seq()
164 	wl1251_reg_write32(wl, 0x00305844, tmp);  in wl1251_boot_init_seq()
174 	tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |  in wl1251_boot_init_seq()
176 	wl1251_reg_write32(wl, 0x00305854, tmp);  in wl1251_boot_init_seq()
182 	tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;  in wl1251_boot_init_seq()
183 	wl1251_reg_write32(wl, 0x00305858, tmp);  in wl1251_boot_init_seq()
190 	tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;  in wl1251_boot_init_seq()
191 	wl1251_reg_write32(wl, 0x003058f8, tmp);  in wl1251_boot_init_seq()
484 	u32 tmp, boot_data;  in wl1251_boot()  local
510 	tmp = wl1251_reg_read32(wl, SCR_PAD2);  in wl1251_boot()
513 	wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;  in wl1251_boot()
514 	wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;  in wl1251_boot()
515 	tmp = wl1251_reg_read32(wl, SCR_PAD3);  in wl1251_boot()
518 	wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;  in wl1251_boot()
519 	minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;  in wl1251_boot()