Lines Matching refs:FIELD32
74 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
75 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
84 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
85 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
86 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
93 #define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002)
99 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
100 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
101 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
102 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
103 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
104 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
105 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
106 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
107 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
108 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
114 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
115 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
116 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
117 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
118 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
119 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
120 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
121 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
122 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
123 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
193 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
194 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
195 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
196 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
233 #define MAC_CSR0_REVISION FIELD32(0x0000000f)
234 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
243 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
244 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
245 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
251 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
252 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
253 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
254 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
265 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
266 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
267 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
273 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
274 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
275 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
276 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
290 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
291 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
292 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
298 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
310 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
311 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
312 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
322 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
323 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
324 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
325 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
339 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
340 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
341 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
342 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
351 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
352 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
353 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
354 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
362 #define MAC_CSR13_VAL0 FIELD32(0x00000001)
363 #define MAC_CSR13_VAL1 FIELD32(0x00000002)
364 #define MAC_CSR13_VAL2 FIELD32(0x00000004)
365 #define MAC_CSR13_VAL3 FIELD32(0x00000008)
366 #define MAC_CSR13_VAL4 FIELD32(0x00000010)
367 #define MAC_CSR13_VAL5 FIELD32(0x00000020)
368 #define MAC_CSR13_DIR0 FIELD32(0x00000100)
369 #define MAC_CSR13_DIR1 FIELD32(0x00000200)
370 #define MAC_CSR13_DIR2 FIELD32(0x00000400)
371 #define MAC_CSR13_DIR3 FIELD32(0x00000800)
372 #define MAC_CSR13_DIR4 FIELD32(0x00001000)
373 #define MAC_CSR13_DIR5 FIELD32(0x00002000)
384 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
385 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
386 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
387 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
388 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
389 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
417 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
418 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
419 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
420 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
421 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
422 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
423 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
424 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
425 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
426 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
427 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
428 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
429 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
430 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
436 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
437 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
438 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
439 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
440 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
441 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
442 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
443 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
449 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
450 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
451 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
452 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
453 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
454 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
455 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
456 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
462 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
463 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
464 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
465 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
466 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
467 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
468 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
469 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
479 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
480 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
481 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
482 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
483 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
484 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
485 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
486 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
487 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
488 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
504 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
505 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
506 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
507 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
513 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
514 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
515 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
516 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
526 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
527 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
528 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
529 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
530 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
531 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
547 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
553 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
574 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
575 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
595 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
596 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
597 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
598 #define PHY_CSR3_BUSY FIELD32(0x00010000)
609 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
610 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
611 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
612 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
613 #define PHY_CSR4_BUSY FIELD32(0x80000000)
619 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
625 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
640 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
641 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
642 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
643 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
644 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
645 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
646 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
647 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
648 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
649 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
650 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
651 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
652 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
653 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
654 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
655 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
661 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
662 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
663 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
664 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
665 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
666 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
667 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
668 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
682 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
683 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
684 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
685 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
691 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
692 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
693 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
694 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
695 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
696 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
697 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
698 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
708 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
709 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
715 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
716 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
722 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
723 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
729 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
736 #define STA_CSR4_VALID FIELD32(0x00000001)
737 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
738 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
739 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
740 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
741 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
751 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
752 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
753 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
754 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
760 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
761 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
789 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
795 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
801 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
807 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
813 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
819 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
820 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
821 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
822 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
829 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
830 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
831 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
841 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
842 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
843 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
844 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
854 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
855 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
856 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
857 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
867 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
868 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
869 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
870 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
877 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
878 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
879 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
880 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
881 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
895 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
896 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
897 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
898 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
899 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
900 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
901 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
902 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
903 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
904 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
910 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
911 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
912 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
913 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
914 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
929 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
936 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
937 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
938 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
944 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
945 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
967 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
968 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
969 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
970 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
971 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
972 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
973 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
974 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
975 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
976 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
983 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
984 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
985 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
986 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
987 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
988 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
989 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
990 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
991 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
992 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
993 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
994 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
1003 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
1004 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
1005 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
1006 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
1007 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
1008 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
1009 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
1017 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
1018 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1026 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1027 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1064 #define IO_CNTL_CSR_RF_PS FIELD32(0x00000004)
1141 #define RF3_TXPOWER FIELD32(0x00003e00)
1146 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1310 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1311 #define TXD_W0_VALID FIELD32(0x00000002)
1312 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1313 #define TXD_W0_ACK FIELD32(0x00000008)
1314 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1315 #define TXD_W0_OFDM FIELD32(0x00000020)
1316 #define TXD_W0_IFS FIELD32(0x00000040)
1317 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1318 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1319 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1320 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1321 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1322 #define TXD_W0_BURST FIELD32(0x10000000)
1323 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1331 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1332 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1333 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1334 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1335 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1336 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1337 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1338 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1343 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1344 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1345 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1346 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1351 #define TXD_W3_IV FIELD32(0xffffffff)
1356 #define TXD_W4_EIV FIELD32(0xffffffff)
1366 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1367 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1368 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1369 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1370 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1385 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1386 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1387 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1388 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1389 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1394 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1395 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1396 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1397 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1398 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1403 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1408 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1419 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1420 #define RXD_W0_DROP FIELD32(0x00000002)
1421 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1422 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1423 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1424 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1425 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1426 #define RXD_W0_OFDM FIELD32(0x00000080)
1427 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1428 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1429 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1430 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1436 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1437 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1438 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1439 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1445 #define RXD_W2_IV FIELD32(0xffffffff)
1451 #define RXD_W3_EIV FIELD32(0xffffffff)
1458 #define RXD_W4_ICV FIELD32(0xffffffff)
1470 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1475 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1476 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1477 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1478 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1479 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1480 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1481 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1482 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1483 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1484 #define RXD_W15_RESERVED FIELD32(0xffffffff)