Lines Matching refs:rt2x00dev
56 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt2500pci_bbp_write() argument
61 mutex_lock(&rt2x00dev->csr_mutex); in rt2500pci_bbp_write()
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write()
77 mutex_unlock(&rt2x00dev->csr_mutex); in rt2500pci_bbp_write()
80 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt2500pci_bbp_read() argument
85 mutex_lock(&rt2x00dev->csr_mutex); in rt2500pci_bbp_read()
95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_read()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_read()
103 WAIT_FOR_BBP(rt2x00dev, ®); in rt2500pci_bbp_read()
108 mutex_unlock(&rt2x00dev->csr_mutex); in rt2500pci_bbp_read()
111 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt2500pci_rf_write() argument
116 mutex_lock(&rt2x00dev->csr_mutex); in rt2500pci_rf_write()
122 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2500pci_rf_write()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2500pci_rf_write()
130 rt2x00_rf_write(rt2x00dev, word, value); in rt2500pci_rf_write()
133 mutex_unlock(&rt2x00dev->csr_mutex); in rt2500pci_rf_write()
138 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2500pci_eepromregister_read() local
141 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2500pci_eepromregister_read()
153 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2500pci_eepromregister_write() local
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2500pci_eepromregister_write()
201 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt2500pci_rfkill_poll() argument
205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2500pci_rfkill_poll()
218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2500pci_brightness_set()
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2500pci_brightness_set()
236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2500pci_blink_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2500pci_blink_set()
244 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev, in rt2500pci_init_led() argument
248 led->rt2x00dev = rt2x00dev; in rt2500pci_init_led()
259 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_filter() argument
270 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2500pci_config_filter()
279 !rt2x00dev->intf_ap_count); in rt2500pci_config_filter()
284 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_config_filter()
287 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_intf() argument
292 struct data_queue *queue = rt2x00dev->bcn; in rt2500pci_config_intf()
301 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®); in rt2500pci_config_intf()
304 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2500pci_config_intf()
309 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_config_intf()
311 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_config_intf()
315 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, in rt2500pci_config_intf()
319 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, in rt2500pci_config_intf()
323 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_erp() argument
336 rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®); in rt2500pci_config_erp()
341 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2500pci_config_erp()
343 rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®); in rt2500pci_config_erp()
348 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2500pci_config_erp()
350 rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®); in rt2500pci_config_erp()
355 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2500pci_config_erp()
357 rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®); in rt2500pci_config_erp()
362 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2500pci_config_erp()
364 rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®); in rt2500pci_config_erp()
369 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2500pci_config_erp()
373 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); in rt2500pci_config_erp()
376 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2500pci_config_erp()
378 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_config_erp()
380 rt2x00mmio_register_read(rt2x00dev, CSR18, ®); in rt2500pci_config_erp()
383 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2500pci_config_erp()
385 rt2x00mmio_register_read(rt2x00dev, CSR19, ®); in rt2500pci_config_erp()
388 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2500pci_config_erp()
392 rt2x00mmio_register_read(rt2x00dev, CSR12, ®); in rt2500pci_config_erp()
397 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2500pci_config_erp()
402 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_ant() argument
416 rt2x00mmio_register_read(rt2x00dev, BBPCSR1, ®); in rt2500pci_config_ant()
417 rt2500pci_bbp_read(rt2x00dev, 14, &r14); in rt2500pci_config_ant()
418 rt2500pci_bbp_read(rt2x00dev, 2, &r2); in rt2500pci_config_ant()
453 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) { in rt2500pci_config_ant()
461 if (rt2x00_rf(rt2x00dev, RF2525E)) in rt2500pci_config_ant()
468 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); in rt2500pci_config_ant()
469 rt2500pci_bbp_write(rt2x00dev, 14, r14); in rt2500pci_config_ant()
470 rt2500pci_bbp_write(rt2x00dev, 2, r2); in rt2500pci_config_ant()
473 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_channel() argument
487 if (!rt2x00_rf(rt2x00dev, RF2523)) in rt2500pci_config_channel()
494 if (rt2x00_rf(rt2x00dev, RF2525)) { in rt2500pci_config_channel()
502 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2500pci_config_channel()
503 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]); in rt2500pci_config_channel()
504 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2500pci_config_channel()
506 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); in rt2500pci_config_channel()
509 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2500pci_config_channel()
510 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2500pci_config_channel()
511 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2500pci_config_channel()
513 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); in rt2500pci_config_channel()
520 rt2500pci_bbp_write(rt2x00dev, 70, r70); in rt2500pci_config_channel()
528 if (!rt2x00_rf(rt2x00dev, RF2523)) { in rt2500pci_config_channel()
530 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2500pci_config_channel()
534 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2500pci_config_channel()
539 rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1); in rt2500pci_config_channel()
542 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_txpower() argument
547 rt2x00_rf_read(rt2x00dev, 3, &rf3); in rt2500pci_config_txpower()
549 rt2500pci_rf_write(rt2x00dev, 3, rf3); in rt2500pci_config_txpower()
552 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_retry_limit() argument
557 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2500pci_config_retry_limit()
562 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_config_retry_limit()
565 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt2500pci_config_ps() argument
574 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2500pci_config_ps()
576 (rt2x00dev->beacon_int - 20) * 16); in rt2500pci_config_ps()
582 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
585 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
587 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2500pci_config_ps()
589 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
592 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); in rt2500pci_config_ps()
595 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev, in rt2500pci_config() argument
600 rt2500pci_config_channel(rt2x00dev, &libconf->rf, in rt2500pci_config()
604 rt2500pci_config_txpower(rt2x00dev, in rt2500pci_config()
607 rt2500pci_config_retry_limit(rt2x00dev, libconf); in rt2500pci_config()
609 rt2500pci_config_ps(rt2x00dev, libconf); in rt2500pci_config()
615 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt2500pci_link_stats() argument
623 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2500pci_link_stats()
629 rt2x00mmio_register_read(rt2x00dev, CNT3, ®); in rt2500pci_link_stats()
633 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt2500pci_set_vgc() argument
637 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level); in rt2500pci_set_vgc()
643 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt2500pci_reset_tuner() argument
646 rt2500pci_set_vgc(rt2x00dev, qual, 0x48); in rt2500pci_reset_tuner()
649 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt2500pci_link_tuner() argument
657 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D && in rt2500pci_link_tuner()
658 rt2x00dev->intf_associated && count > 20) in rt2500pci_link_tuner()
667 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D || in rt2500pci_link_tuner()
668 !rt2x00dev->intf_associated) in rt2500pci_link_tuner()
678 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); in rt2500pci_link_tuner()
686 rt2500pci_set_vgc(rt2x00dev, qual, 0x50); in rt2500pci_link_tuner()
694 rt2500pci_set_vgc(rt2x00dev, qual, 0x41); in rt2500pci_link_tuner()
703 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); in rt2500pci_link_tuner()
714 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg); in rt2500pci_link_tuner()
716 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg); in rt2500pci_link_tuner()
724 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2500pci_start_queue() local
729 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2500pci_start_queue()
731 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_start_queue()
734 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_start_queue()
738 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_start_queue()
747 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2500pci_kick_queue() local
752 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_kick_queue()
754 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
757 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_kick_queue()
759 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
762 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_kick_queue()
764 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
773 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2500pci_stop_queue() local
780 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_stop_queue()
782 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_stop_queue()
785 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2500pci_stop_queue()
787 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_stop_queue()
790 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_stop_queue()
794 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_stop_queue()
799 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2500pci_stop_queue()
848 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt2500pci_init_queues() argument
856 rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®); in rt2500pci_init_queues()
857 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2500pci_init_queues()
858 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2500pci_init_queues()
859 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2500pci_init_queues()
860 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2500pci_init_queues()
861 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2500pci_init_queues()
863 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt2500pci_init_queues()
864 rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®); in rt2500pci_init_queues()
867 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2500pci_init_queues()
869 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt2500pci_init_queues()
870 rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®); in rt2500pci_init_queues()
873 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2500pci_init_queues()
875 entry_priv = rt2x00dev->atim->entries[0].priv_data; in rt2500pci_init_queues()
876 rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®); in rt2500pci_init_queues()
879 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2500pci_init_queues()
881 entry_priv = rt2x00dev->bcn->entries[0].priv_data; in rt2500pci_init_queues()
882 rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®); in rt2500pci_init_queues()
885 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2500pci_init_queues()
887 rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®); in rt2500pci_init_queues()
888 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2500pci_init_queues()
889 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2500pci_init_queues()
890 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2500pci_init_queues()
892 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt2500pci_init_queues()
893 rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®); in rt2500pci_init_queues()
896 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2500pci_init_queues()
901 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt2500pci_init_registers() argument
905 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); in rt2500pci_init_registers()
906 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); in rt2500pci_init_registers()
907 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002); in rt2500pci_init_registers()
908 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); in rt2500pci_init_registers()
910 rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®); in rt2500pci_init_registers()
914 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2500pci_init_registers()
916 rt2x00mmio_register_read(rt2x00dev, CSR9, ®); in rt2500pci_init_registers()
918 rt2x00dev->rx->data_size / 128); in rt2500pci_init_registers()
919 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2500pci_init_registers()
924 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2500pci_init_registers()
926 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_init_registers()
928 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_init_registers()
937 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_init_registers()
939 rt2x00mmio_register_write(rt2x00dev, CNT3, 0); in rt2500pci_init_registers()
941 rt2x00mmio_register_read(rt2x00dev, TXCSR8, ®); in rt2500pci_init_registers()
950 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); in rt2500pci_init_registers()
952 rt2x00mmio_register_read(rt2x00dev, ARTCSR0, ®); in rt2500pci_init_registers()
957 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); in rt2500pci_init_registers()
959 rt2x00mmio_register_read(rt2x00dev, ARTCSR1, ®); in rt2500pci_init_registers()
964 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); in rt2500pci_init_registers()
966 rt2x00mmio_register_read(rt2x00dev, ARTCSR2, ®); in rt2500pci_init_registers()
971 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); in rt2500pci_init_registers()
973 rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®); in rt2500pci_init_registers()
982 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2500pci_init_registers()
984 rt2x00mmio_register_read(rt2x00dev, PCICSR, ®); in rt2500pci_init_registers()
992 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); in rt2500pci_init_registers()
994 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); in rt2500pci_init_registers()
996 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); in rt2500pci_init_registers()
997 rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0); in rt2500pci_init_registers()
999 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt2500pci_init_registers()
1002 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223); in rt2500pci_init_registers()
1003 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); in rt2500pci_init_registers()
1005 rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®); in rt2500pci_init_registers()
1007 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2500pci_init_registers()
1009 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®); in rt2500pci_init_registers()
1016 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2500pci_init_registers()
1018 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200); in rt2500pci_init_registers()
1020 rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020); in rt2500pci_init_registers()
1022 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2500pci_init_registers()
1026 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1028 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2500pci_init_registers()
1031 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1038 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2500pci_init_registers()
1039 rt2x00mmio_register_read(rt2x00dev, CNT4, ®); in rt2500pci_init_registers()
1044 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt2500pci_wait_bbp_ready() argument
1050 rt2500pci_bbp_read(rt2x00dev, 0, &value); in rt2500pci_wait_bbp_ready()
1056 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt2500pci_wait_bbp_ready()
1060 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt2500pci_init_bbp() argument
1067 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev))) in rt2500pci_init_bbp()
1070 rt2500pci_bbp_write(rt2x00dev, 3, 0x02); in rt2500pci_init_bbp()
1071 rt2500pci_bbp_write(rt2x00dev, 4, 0x19); in rt2500pci_init_bbp()
1072 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); in rt2500pci_init_bbp()
1073 rt2500pci_bbp_write(rt2x00dev, 15, 0x30); in rt2500pci_init_bbp()
1074 rt2500pci_bbp_write(rt2x00dev, 16, 0xac); in rt2500pci_init_bbp()
1075 rt2500pci_bbp_write(rt2x00dev, 18, 0x18); in rt2500pci_init_bbp()
1076 rt2500pci_bbp_write(rt2x00dev, 19, 0xff); in rt2500pci_init_bbp()
1077 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); in rt2500pci_init_bbp()
1078 rt2500pci_bbp_write(rt2x00dev, 21, 0x08); in rt2500pci_init_bbp()
1079 rt2500pci_bbp_write(rt2x00dev, 22, 0x08); in rt2500pci_init_bbp()
1080 rt2500pci_bbp_write(rt2x00dev, 23, 0x08); in rt2500pci_init_bbp()
1081 rt2500pci_bbp_write(rt2x00dev, 24, 0x70); in rt2500pci_init_bbp()
1082 rt2500pci_bbp_write(rt2x00dev, 25, 0x40); in rt2500pci_init_bbp()
1083 rt2500pci_bbp_write(rt2x00dev, 26, 0x08); in rt2500pci_init_bbp()
1084 rt2500pci_bbp_write(rt2x00dev, 27, 0x23); in rt2500pci_init_bbp()
1085 rt2500pci_bbp_write(rt2x00dev, 30, 0x10); in rt2500pci_init_bbp()
1086 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); in rt2500pci_init_bbp()
1087 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); in rt2500pci_init_bbp()
1088 rt2500pci_bbp_write(rt2x00dev, 34, 0x12); in rt2500pci_init_bbp()
1089 rt2500pci_bbp_write(rt2x00dev, 35, 0x50); in rt2500pci_init_bbp()
1090 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); in rt2500pci_init_bbp()
1091 rt2500pci_bbp_write(rt2x00dev, 40, 0x02); in rt2500pci_init_bbp()
1092 rt2500pci_bbp_write(rt2x00dev, 41, 0x60); in rt2500pci_init_bbp()
1093 rt2500pci_bbp_write(rt2x00dev, 53, 0x10); in rt2500pci_init_bbp()
1094 rt2500pci_bbp_write(rt2x00dev, 54, 0x18); in rt2500pci_init_bbp()
1095 rt2500pci_bbp_write(rt2x00dev, 56, 0x08); in rt2500pci_init_bbp()
1096 rt2500pci_bbp_write(rt2x00dev, 57, 0x10); in rt2500pci_init_bbp()
1097 rt2500pci_bbp_write(rt2x00dev, 58, 0x08); in rt2500pci_init_bbp()
1098 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); in rt2500pci_init_bbp()
1099 rt2500pci_bbp_write(rt2x00dev, 62, 0x10); in rt2500pci_init_bbp()
1102 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); in rt2500pci_init_bbp()
1107 rt2500pci_bbp_write(rt2x00dev, reg_id, value); in rt2500pci_init_bbp()
1117 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt2500pci_toggle_irq() argument
1129 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2500pci_toggle_irq()
1130 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_toggle_irq()
1137 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt2500pci_toggle_irq()
1139 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_toggle_irq()
1145 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_toggle_irq()
1147 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt2500pci_toggle_irq()
1153 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt2500pci_toggle_irq()
1154 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt2500pci_toggle_irq()
1155 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2500pci_toggle_irq()
1159 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt2500pci_enable_radio() argument
1164 if (unlikely(rt2500pci_init_queues(rt2x00dev) || in rt2500pci_enable_radio()
1165 rt2500pci_init_registers(rt2x00dev) || in rt2500pci_enable_radio()
1166 rt2500pci_init_bbp(rt2x00dev))) in rt2500pci_enable_radio()
1172 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt2500pci_disable_radio() argument
1177 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); in rt2500pci_disable_radio()
1180 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, in rt2500pci_set_state() argument
1191 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®); in rt2500pci_set_state()
1196 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2500pci_set_state()
1204 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®2); in rt2500pci_set_state()
1209 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2500pci_set_state()
1216 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt2500pci_set_device_state() argument
1223 retval = rt2500pci_enable_radio(rt2x00dev); in rt2500pci_set_device_state()
1226 rt2500pci_disable_radio(rt2x00dev); in rt2500pci_set_device_state()
1230 rt2500pci_toggle_irq(rt2x00dev, state); in rt2500pci_set_device_state()
1236 retval = rt2500pci_set_state(rt2x00dev, state); in rt2500pci_set_device_state()
1244 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt2500pci_set_device_state()
1326 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2500pci_write_beacon() local
1333 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_write_beacon()
1335 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_write_beacon()
1338 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); in rt2500pci_write_beacon()
1350 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); in rt2500pci_write_beacon()
1356 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_write_beacon()
1385 entry->queue->rt2x00dev->rssi_offset; in rt2500pci_fill_rxdone()
1399 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, in rt2500pci_txdone() argument
1402 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt2500pci_txdone()
1438 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt2500pci_enable_interrupt() argument
1447 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2500pci_enable_interrupt()
1449 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_enable_interrupt()
1451 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_enable_interrupt()
1453 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2500pci_enable_interrupt()
1458 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2500pci_txstatus_tasklet() local
1464 rt2500pci_txdone(rt2x00dev, QID_ATIM); in rt2500pci_txstatus_tasklet()
1465 rt2500pci_txdone(rt2x00dev, QID_AC_VO); in rt2500pci_txstatus_tasklet()
1466 rt2500pci_txdone(rt2x00dev, QID_AC_VI); in rt2500pci_txstatus_tasklet()
1471 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { in rt2500pci_txstatus_tasklet()
1472 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2500pci_txstatus_tasklet()
1474 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_txstatus_tasklet()
1478 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_txstatus_tasklet()
1480 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2500pci_txstatus_tasklet()
1486 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2500pci_tbtt_tasklet() local
1487 rt2x00lib_beacondone(rt2x00dev); in rt2500pci_tbtt_tasklet()
1488 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2500pci_tbtt_tasklet()
1489 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); in rt2500pci_tbtt_tasklet()
1494 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2500pci_rxdone_tasklet() local
1495 if (rt2x00mmio_rxdone(rt2x00dev)) in rt2500pci_rxdone_tasklet()
1496 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2500pci_rxdone_tasklet()
1497 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2500pci_rxdone_tasklet()
1498 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); in rt2500pci_rxdone_tasklet()
1503 struct rt2x00_dev *rt2x00dev = dev_instance; in rt2500pci_interrupt() local
1510 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2500pci_interrupt()
1511 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_interrupt()
1516 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2500pci_interrupt()
1525 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt2500pci_interrupt()
1528 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2500pci_interrupt()
1533 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt2500pci_interrupt()
1546 spin_lock(&rt2x00dev->irqmask_lock); in rt2500pci_interrupt()
1548 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_interrupt()
1550 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_interrupt()
1552 spin_unlock(&rt2x00dev->irqmask_lock); in rt2500pci_interrupt()
1560 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt2500pci_validate_eeprom() argument
1567 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2500pci_validate_eeprom()
1569 eeprom.data = rt2x00dev; in rt2500pci_validate_eeprom()
1579 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt2500pci_validate_eeprom()
1585 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt2500pci_validate_eeprom()
1588 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); in rt2500pci_validate_eeprom()
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); in rt2500pci_validate_eeprom()
1603 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); in rt2500pci_validate_eeprom()
1604 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); in rt2500pci_validate_eeprom()
1607 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); in rt2500pci_validate_eeprom()
1612 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); in rt2500pci_validate_eeprom()
1613 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); in rt2500pci_validate_eeprom()
1616 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word); in rt2500pci_validate_eeprom()
1620 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word); in rt2500pci_validate_eeprom()
1621 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n", in rt2500pci_validate_eeprom()
1628 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt2500pci_init_eeprom() argument
1637 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); in rt2500pci_init_eeprom()
1643 rt2x00mmio_register_read(rt2x00dev, CSR0, ®); in rt2500pci_init_eeprom()
1644 rt2x00_set_chip(rt2x00dev, RT2560, value, in rt2500pci_init_eeprom()
1647 if (!rt2x00_rf(rt2x00dev, RF2522) && in rt2500pci_init_eeprom()
1648 !rt2x00_rf(rt2x00dev, RF2523) && in rt2500pci_init_eeprom()
1649 !rt2x00_rf(rt2x00dev, RF2524) && in rt2500pci_init_eeprom()
1650 !rt2x00_rf(rt2x00dev, RF2525) && in rt2500pci_init_eeprom()
1651 !rt2x00_rf(rt2x00dev, RF2525E) && in rt2500pci_init_eeprom()
1652 !rt2x00_rf(rt2x00dev, RF5222)) { in rt2500pci_init_eeprom()
1653 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt2500pci_init_eeprom()
1660 rt2x00dev->default_ant.tx = in rt2500pci_init_eeprom()
1662 rt2x00dev->default_ant.rx = in rt2500pci_init_eeprom()
1671 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt2500pci_init_eeprom()
1675 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt2500pci_init_eeprom()
1683 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt2500pci_init_eeprom()
1687 __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags); in rt2500pci_init_eeprom()
1693 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); in rt2500pci_init_eeprom()
1695 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt2500pci_init_eeprom()
1700 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom); in rt2500pci_init_eeprom()
1701 rt2x00dev->rssi_offset = in rt2500pci_init_eeprom()
1862 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt2500pci_probe_hw_mode() argument
1864 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt2500pci_probe_hw_mode()
1872 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt2500pci_probe_hw_mode()
1873 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt2500pci_probe_hw_mode()
1874 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt2500pci_probe_hw_mode()
1875 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt2500pci_probe_hw_mode()
1877 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt2500pci_probe_hw_mode()
1878 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt2500pci_probe_hw_mode()
1879 rt2x00_eeprom_addr(rt2x00dev, in rt2500pci_probe_hw_mode()
1885 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; in rt2500pci_probe_hw_mode()
1893 if (rt2x00_rf(rt2x00dev, RF2522)) { in rt2500pci_probe_hw_mode()
1896 } else if (rt2x00_rf(rt2x00dev, RF2523)) { in rt2500pci_probe_hw_mode()
1899 } else if (rt2x00_rf(rt2x00dev, RF2524)) { in rt2500pci_probe_hw_mode()
1902 } else if (rt2x00_rf(rt2x00dev, RF2525)) { in rt2500pci_probe_hw_mode()
1905 } else if (rt2x00_rf(rt2x00dev, RF2525E)) { in rt2500pci_probe_hw_mode()
1908 } else if (rt2x00_rf(rt2x00dev, RF5222)) { in rt2500pci_probe_hw_mode()
1923 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); in rt2500pci_probe_hw_mode()
1939 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt2500pci_probe_hw() argument
1947 retval = rt2500pci_validate_eeprom(rt2x00dev); in rt2500pci_probe_hw()
1951 retval = rt2500pci_init_eeprom(rt2x00dev); in rt2500pci_probe_hw()
1959 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2500pci_probe_hw()
1961 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2500pci_probe_hw()
1966 retval = rt2500pci_probe_hw_mode(rt2x00dev); in rt2500pci_probe_hw()
1973 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); in rt2500pci_probe_hw()
1974 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt2500pci_probe_hw()
1975 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); in rt2500pci_probe_hw()
1980 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt2500pci_probe_hw()
1991 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2500pci_get_tsf() local
1995 rt2x00mmio_register_read(rt2x00dev, CSR17, ®); in rt2500pci_get_tsf()
1997 rt2x00mmio_register_read(rt2x00dev, CSR16, ®); in rt2500pci_get_tsf()
2005 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2500pci_tx_last_beacon() local
2008 rt2x00mmio_register_read(rt2x00dev, CSR15, ®); in rt2500pci_tx_last_beacon()