Lines Matching refs:rt2x00dev
56 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt2400pci_bbp_write() argument
61 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_write()
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
77 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_write()
80 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt2400pci_bbp_read() argument
85 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_read()
95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_read()
103 WAIT_FOR_BBP(rt2x00dev, ®); in rt2400pci_bbp_read()
108 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_read()
111 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt2400pci_rf_write() argument
116 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_rf_write()
122 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2400pci_rf_write()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2400pci_rf_write()
130 rt2x00_rf_write(rt2x00dev, word, value); in rt2400pci_rf_write()
133 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_rf_write()
138 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2400pci_eepromregister_read() local
141 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2400pci_eepromregister_read()
153 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2400pci_eepromregister_write() local
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2400pci_eepromregister_write()
201 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt2400pci_rfkill_poll() argument
205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2400pci_rfkill_poll()
218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2400pci_brightness_set()
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_brightness_set()
236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2400pci_blink_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_blink_set()
244 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev, in rt2400pci_init_led() argument
248 led->rt2x00dev = rt2x00dev; in rt2400pci_init_led()
259 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_filter() argument
269 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2400pci_config_filter()
278 !rt2x00dev->intf_ap_count); in rt2400pci_config_filter()
280 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_config_filter()
283 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_intf() argument
296 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®); in rt2400pci_config_intf()
298 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2400pci_config_intf()
303 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_config_intf()
305 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_config_intf()
309 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, in rt2400pci_config_intf()
313 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, in rt2400pci_config_intf()
318 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_erp() argument
331 rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®); in rt2400pci_config_erp()
336 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2400pci_config_erp()
338 rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®); in rt2400pci_config_erp()
343 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2400pci_config_erp()
345 rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®); in rt2400pci_config_erp()
350 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2400pci_config_erp()
352 rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®); in rt2400pci_config_erp()
357 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2400pci_config_erp()
359 rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®); in rt2400pci_config_erp()
364 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2400pci_config_erp()
368 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); in rt2400pci_config_erp()
371 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2400pci_config_erp()
373 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_erp()
375 rt2x00mmio_register_read(rt2x00dev, CSR18, ®); in rt2400pci_config_erp()
378 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2400pci_config_erp()
380 rt2x00mmio_register_read(rt2x00dev, CSR19, ®); in rt2400pci_config_erp()
383 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2400pci_config_erp()
387 rt2x00mmio_register_read(rt2x00dev, CSR12, ®); in rt2400pci_config_erp()
392 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2400pci_config_erp()
396 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_ant() argument
409 rt2400pci_bbp_read(rt2x00dev, 4, &r4); in rt2400pci_config_ant()
410 rt2400pci_bbp_read(rt2x00dev, 1, &r1); in rt2400pci_config_ant()
444 rt2400pci_bbp_write(rt2x00dev, 4, r4); in rt2400pci_config_ant()
445 rt2400pci_bbp_write(rt2x00dev, 1, r1); in rt2400pci_config_ant()
448 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_channel() argument
457 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
458 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2400pci_config_channel()
459 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
464 if (rt2x00_rf(rt2x00dev, RF2420)) in rt2400pci_config_channel()
472 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
473 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32); in rt2400pci_config_channel()
474 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
478 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
479 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2400pci_config_channel()
480 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
490 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
491 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
496 rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1); in rt2400pci_config_channel()
499 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) in rt2400pci_config_txpower() argument
501 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower)); in rt2400pci_config_txpower()
504 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_retry_limit() argument
509 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2400pci_config_retry_limit()
514 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_retry_limit()
517 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_ps() argument
526 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2400pci_config_ps()
528 (rt2x00dev->beacon_int - 20) * 16); in rt2400pci_config_ps()
534 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
537 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
539 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2400pci_config_ps()
541 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
544 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); in rt2400pci_config_ps()
547 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, in rt2400pci_config() argument
552 rt2400pci_config_channel(rt2x00dev, &libconf->rf); in rt2400pci_config()
554 rt2400pci_config_txpower(rt2x00dev, in rt2400pci_config()
557 rt2400pci_config_retry_limit(rt2x00dev, libconf); in rt2400pci_config()
559 rt2400pci_config_ps(rt2x00dev, libconf); in rt2400pci_config()
562 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_cw() argument
567 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2400pci_config_cw()
570 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_cw()
576 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt2400pci_link_stats() argument
585 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2400pci_link_stats()
591 rt2400pci_bbp_read(rt2x00dev, 39, &bbp); in rt2400pci_link_stats()
595 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_vgc() argument
599 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level); in rt2400pci_set_vgc()
605 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt2400pci_reset_tuner() argument
608 rt2400pci_set_vgc(rt2x00dev, qual, 0x08); in rt2400pci_reset_tuner()
611 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt2400pci_link_tuner() argument
625 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt2400pci_link_tuner()
627 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt2400pci_link_tuner()
635 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_start_queue() local
640 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2400pci_start_queue()
642 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_start_queue()
645 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_start_queue()
649 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_start_queue()
658 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_kick_queue() local
663 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_kick_queue()
665 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
668 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_kick_queue()
670 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
673 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_kick_queue()
675 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
684 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_stop_queue() local
691 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2400pci_stop_queue()
693 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_stop_queue()
696 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2400pci_stop_queue()
698 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_stop_queue()
701 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_stop_queue()
705 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_stop_queue()
710 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2400pci_stop_queue()
763 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_queues() argument
771 rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®); in rt2400pci_init_queues()
772 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
773 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
774 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
775 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
776 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2400pci_init_queues()
778 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt2400pci_init_queues()
779 rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®); in rt2400pci_init_queues()
782 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2400pci_init_queues()
784 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt2400pci_init_queues()
785 rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®); in rt2400pci_init_queues()
788 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2400pci_init_queues()
790 entry_priv = rt2x00dev->atim->entries[0].priv_data; in rt2400pci_init_queues()
791 rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®); in rt2400pci_init_queues()
794 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2400pci_init_queues()
796 entry_priv = rt2x00dev->bcn->entries[0].priv_data; in rt2400pci_init_queues()
797 rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®); in rt2400pci_init_queues()
800 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2400pci_init_queues()
802 rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®); in rt2400pci_init_queues()
803 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
804 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
805 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2400pci_init_queues()
807 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt2400pci_init_queues()
808 rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®); in rt2400pci_init_queues()
811 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2400pci_init_queues()
816 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_registers() argument
820 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); in rt2400pci_init_registers()
821 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); in rt2400pci_init_registers()
822 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20); in rt2400pci_init_registers()
823 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); in rt2400pci_init_registers()
825 rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®); in rt2400pci_init_registers()
829 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2400pci_init_registers()
831 rt2x00mmio_register_read(rt2x00dev, CSR9, ®); in rt2400pci_init_registers()
833 (rt2x00dev->rx->data_size / 128)); in rt2400pci_init_registers()
834 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2400pci_init_registers()
836 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_init_registers()
845 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_init_registers()
847 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000); in rt2400pci_init_registers()
849 rt2x00mmio_register_read(rt2x00dev, ARCSR0, ®); in rt2400pci_init_registers()
854 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); in rt2400pci_init_registers()
856 rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®); in rt2400pci_init_registers()
863 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2400pci_init_registers()
865 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); in rt2400pci_init_registers()
867 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt2400pci_init_registers()
870 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223); in rt2400pci_init_registers()
871 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); in rt2400pci_init_registers()
873 rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®); in rt2400pci_init_registers()
875 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2400pci_init_registers()
877 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®); in rt2400pci_init_registers()
882 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2400pci_init_registers()
884 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2400pci_init_registers()
888 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
890 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2400pci_init_registers()
893 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
900 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2400pci_init_registers()
901 rt2x00mmio_register_read(rt2x00dev, CNT4, ®); in rt2400pci_init_registers()
906 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt2400pci_wait_bbp_ready() argument
912 rt2400pci_bbp_read(rt2x00dev, 0, &value); in rt2400pci_wait_bbp_ready()
918 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt2400pci_wait_bbp_ready()
922 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_bbp() argument
929 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev))) in rt2400pci_init_bbp()
932 rt2400pci_bbp_write(rt2x00dev, 1, 0x00); in rt2400pci_init_bbp()
933 rt2400pci_bbp_write(rt2x00dev, 3, 0x27); in rt2400pci_init_bbp()
934 rt2400pci_bbp_write(rt2x00dev, 4, 0x08); in rt2400pci_init_bbp()
935 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f); in rt2400pci_init_bbp()
936 rt2400pci_bbp_write(rt2x00dev, 15, 0x72); in rt2400pci_init_bbp()
937 rt2400pci_bbp_write(rt2x00dev, 16, 0x74); in rt2400pci_init_bbp()
938 rt2400pci_bbp_write(rt2x00dev, 17, 0x20); in rt2400pci_init_bbp()
939 rt2400pci_bbp_write(rt2x00dev, 18, 0x72); in rt2400pci_init_bbp()
940 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b); in rt2400pci_init_bbp()
941 rt2400pci_bbp_write(rt2x00dev, 20, 0x00); in rt2400pci_init_bbp()
942 rt2400pci_bbp_write(rt2x00dev, 28, 0x11); in rt2400pci_init_bbp()
943 rt2400pci_bbp_write(rt2x00dev, 29, 0x04); in rt2400pci_init_bbp()
944 rt2400pci_bbp_write(rt2x00dev, 30, 0x21); in rt2400pci_init_bbp()
945 rt2400pci_bbp_write(rt2x00dev, 31, 0x00); in rt2400pci_init_bbp()
948 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); in rt2400pci_init_bbp()
953 rt2400pci_bbp_write(rt2x00dev, reg_id, value); in rt2400pci_init_bbp()
963 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt2400pci_toggle_irq() argument
975 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2400pci_toggle_irq()
976 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
983 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt2400pci_toggle_irq()
985 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_toggle_irq()
991 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
993 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt2400pci_toggle_irq()
1000 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt2400pci_toggle_irq()
1001 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt2400pci_toggle_irq()
1002 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2400pci_toggle_irq()
1006 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt2400pci_enable_radio() argument
1011 if (unlikely(rt2400pci_init_queues(rt2x00dev) || in rt2400pci_enable_radio()
1012 rt2400pci_init_registers(rt2x00dev) || in rt2400pci_enable_radio()
1013 rt2400pci_init_bbp(rt2x00dev))) in rt2400pci_enable_radio()
1019 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt2400pci_disable_radio() argument
1024 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); in rt2400pci_disable_radio()
1027 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_state() argument
1038 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®); in rt2400pci_set_state()
1043 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1051 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®2); in rt2400pci_set_state()
1056 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1063 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_device_state() argument
1070 retval = rt2400pci_enable_radio(rt2x00dev); in rt2400pci_set_device_state()
1073 rt2400pci_disable_radio(rt2x00dev); in rt2400pci_set_device_state()
1077 rt2400pci_toggle_irq(rt2x00dev, state); in rt2400pci_set_device_state()
1083 retval = rt2400pci_set_state(rt2x00dev, state); in rt2400pci_set_device_state()
1091 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt2400pci_set_device_state()
1174 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2400pci_write_beacon() local
1181 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2400pci_write_beacon()
1183 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1186 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); in rt2400pci_write_beacon()
1201 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); in rt2400pci_write_beacon()
1207 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1216 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2400pci_fill_rxdone() local
1245 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL); in rt2400pci_fill_rxdone()
1260 entry->queue->rt2x00dev->rssi_offset; in rt2400pci_fill_rxdone()
1271 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, in rt2400pci_txdone() argument
1274 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt2400pci_txdone()
1310 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt2400pci_enable_interrupt() argument
1319 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_enable_interrupt()
1321 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_enable_interrupt()
1323 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1325 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_enable_interrupt()
1330 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2400pci_txstatus_tasklet() local
1336 rt2400pci_txdone(rt2x00dev, QID_ATIM); in rt2400pci_txstatus_tasklet()
1337 rt2400pci_txdone(rt2x00dev, QID_AC_VO); in rt2400pci_txstatus_tasklet()
1338 rt2400pci_txdone(rt2x00dev, QID_AC_VI); in rt2400pci_txstatus_tasklet()
1343 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { in rt2400pci_txstatus_tasklet()
1344 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_txstatus_tasklet()
1346 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_txstatus_tasklet()
1350 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1352 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_txstatus_tasklet()
1358 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2400pci_tbtt_tasklet() local
1359 rt2x00lib_beacondone(rt2x00dev); in rt2400pci_tbtt_tasklet()
1360 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_tbtt_tasklet()
1361 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); in rt2400pci_tbtt_tasklet()
1366 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2400pci_rxdone_tasklet() local
1367 if (rt2x00mmio_rxdone(rt2x00dev)) in rt2400pci_rxdone_tasklet()
1368 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2400pci_rxdone_tasklet()
1369 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_rxdone_tasklet()
1370 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); in rt2400pci_rxdone_tasklet()
1375 struct rt2x00_dev *rt2x00dev = dev_instance; in rt2400pci_interrupt() local
1382 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2400pci_interrupt()
1383 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
1388 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_interrupt()
1397 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt2400pci_interrupt()
1400 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2400pci_interrupt()
1405 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt2400pci_interrupt()
1418 spin_lock(&rt2x00dev->irqmask_lock); in rt2400pci_interrupt()
1420 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2400pci_interrupt()
1422 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
1424 spin_unlock(&rt2x00dev->irqmask_lock); in rt2400pci_interrupt()
1434 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt2400pci_validate_eeprom() argument
1441 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2400pci_validate_eeprom()
1443 eeprom.data = rt2x00dev; in rt2400pci_validate_eeprom()
1453 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt2400pci_validate_eeprom()
1459 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt2400pci_validate_eeprom()
1462 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); in rt2400pci_validate_eeprom()
1465 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); in rt2400pci_validate_eeprom()
1467 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n"); in rt2400pci_validate_eeprom()
1474 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_eeprom() argument
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); in rt2400pci_init_eeprom()
1489 rt2x00mmio_register_read(rt2x00dev, CSR0, ®); in rt2400pci_init_eeprom()
1490 rt2x00_set_chip(rt2x00dev, RT2460, value, in rt2400pci_init_eeprom()
1493 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) { in rt2400pci_init_eeprom()
1494 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt2400pci_init_eeprom()
1501 rt2x00dev->default_ant.tx = in rt2400pci_init_eeprom()
1503 rt2x00dev->default_ant.rx = in rt2400pci_init_eeprom()
1512 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) in rt2400pci_init_eeprom()
1513 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; in rt2400pci_init_eeprom()
1514 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY) in rt2400pci_init_eeprom()
1515 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; in rt2400pci_init_eeprom()
1523 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt2400pci_init_eeprom()
1527 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt2400pci_init_eeprom()
1535 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt2400pci_init_eeprom()
1541 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt2400pci_init_eeprom()
1567 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt2400pci_probe_hw_mode() argument
1569 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt2400pci_probe_hw_mode()
1577 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt2400pci_probe_hw_mode()
1578 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt2400pci_probe_hw_mode()
1579 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt2400pci_probe_hw_mode()
1580 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt2400pci_probe_hw_mode()
1582 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt2400pci_probe_hw_mode()
1583 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt2400pci_probe_hw_mode()
1584 rt2x00_eeprom_addr(rt2x00dev, in rt2400pci_probe_hw_mode()
1605 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); in rt2400pci_probe_hw_mode()
1614 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt2400pci_probe_hw() argument
1622 retval = rt2400pci_validate_eeprom(rt2x00dev); in rt2400pci_probe_hw()
1626 retval = rt2400pci_init_eeprom(rt2x00dev); in rt2400pci_probe_hw()
1634 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2400pci_probe_hw()
1636 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2400pci_probe_hw()
1641 retval = rt2400pci_probe_hw_mode(rt2x00dev); in rt2400pci_probe_hw()
1648 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1649 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1650 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1655 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt2400pci_probe_hw()
1667 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_conf_tx() local
1683 rt2400pci_config_cw(rt2x00dev, in rt2400pci_conf_tx()
1684 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max); in rt2400pci_conf_tx()
1692 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_get_tsf() local
1696 rt2x00mmio_register_read(rt2x00dev, CSR17, ®); in rt2400pci_get_tsf()
1698 rt2x00mmio_register_read(rt2x00dev, CSR16, ®); in rt2400pci_get_tsf()
1706 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_tx_last_beacon() local
1709 rt2x00mmio_register_read(rt2x00dev, CSR15, ®); in rt2400pci_tx_last_beacon()