Lines Matching refs:rt2x00_set_field32
69 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
97 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_read()
98 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_read()
99 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2400pci_bbp_read()
124 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2400pci_rf_write()
125 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2400pci_rf_write()
126 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2400pci_rf_write()
127 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2400pci_rf_write()
156 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2400pci_eepromregister_write()
157 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2400pci_eepromregister_write()
158 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2400pci_eepromregister_write()
160 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2400pci_eepromregister_write()
221 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2400pci_brightness_set()
223 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2400pci_brightness_set()
237 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2400pci_blink_set()
238 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2400pci_blink_set()
270 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2400pci_config_filter()
272 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2400pci_config_filter()
274 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2400pci_config_filter()
276 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, 1); in rt2400pci_config_filter()
277 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2400pci_config_filter()
279 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2400pci_config_filter()
297 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2400pci_config_intf()
304 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2400pci_config_intf()
332 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); in rt2400pci_config_erp()
333 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); in rt2400pci_config_erp()
334 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2400pci_config_erp()
335 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2400pci_config_erp()
339 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2400pci_config_erp()
340 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2400pci_config_erp()
341 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
346 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2400pci_config_erp()
347 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2400pci_config_erp()
348 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
353 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2400pci_config_erp()
354 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2400pci_config_erp()
355 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
360 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2400pci_config_erp()
361 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2400pci_config_erp()
362 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
372 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2400pci_config_erp()
376 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2400pci_config_erp()
377 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2400pci_config_erp()
381 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2400pci_config_erp()
382 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2400pci_config_erp()
388 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2400pci_config_erp()
390 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2400pci_config_erp()
454 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); in rt2400pci_config_channel()
455 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); in rt2400pci_config_channel()
487 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); in rt2400pci_config_channel()
488 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); in rt2400pci_config_channel()
510 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2400pci_config_retry_limit()
512 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2400pci_config_retry_limit()
527 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2400pci_config_ps()
529 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2400pci_config_ps()
533 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
536 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2400pci_config_ps()
540 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
568 rt2x00_set_field32(®, CSR11_CWMIN, cw_min); in rt2400pci_config_cw()
569 rt2x00_set_field32(®, CSR11_CWMAX, cw_max); in rt2400pci_config_cw()
641 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2400pci_start_queue()
646 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2400pci_start_queue()
647 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2400pci_start_queue()
648 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_start_queue()
664 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2400pci_kick_queue()
669 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2400pci_kick_queue()
674 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2400pci_kick_queue()
692 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2400pci_stop_queue()
697 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2400pci_stop_queue()
702 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_stop_queue()
703 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_stop_queue()
704 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_stop_queue()
745 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len); in rt2400pci_clear_entry()
749 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); in rt2400pci_clear_entry()
753 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); in rt2400pci_clear_entry()
757 rt2x00_set_field32(&word, TXD_W0_VALID, 0); in rt2400pci_clear_entry()
758 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); in rt2400pci_clear_entry()
772 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
773 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
774 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
775 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
780 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2400pci_init_queues()
786 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2400pci_init_queues()
792 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2400pci_init_queues()
798 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2400pci_init_queues()
803 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
804 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
809 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2400pci_init_queues()
826 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2400pci_init_registers()
827 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2400pci_init_registers()
828 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2400pci_init_registers()
832 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2400pci_init_registers()
837 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_init_registers()
838 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2400pci_init_registers()
839 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_init_registers()
840 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2400pci_init_registers()
841 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2400pci_init_registers()
842 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_init_registers()
843 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2400pci_init_registers()
844 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2400pci_init_registers()
850 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); in rt2400pci_init_registers()
851 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); in rt2400pci_init_registers()
852 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); in rt2400pci_init_registers()
853 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); in rt2400pci_init_registers()
857 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ in rt2400pci_init_registers()
858 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2400pci_init_registers()
859 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ in rt2400pci_init_registers()
860 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2400pci_init_registers()
861 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ in rt2400pci_init_registers()
862 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2400pci_init_registers()
874 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2400pci_init_registers()
878 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2400pci_init_registers()
879 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); in rt2400pci_init_registers()
880 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2400pci_init_registers()
881 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); in rt2400pci_init_registers()
885 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2400pci_init_registers()
886 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2400pci_init_registers()
887 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2400pci_init_registers()
891 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2400pci_init_registers()
892 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2400pci_init_registers()
986 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2400pci_toggle_irq()
987 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2400pci_toggle_irq()
988 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2400pci_toggle_irq()
989 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2400pci_toggle_irq()
990 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2400pci_toggle_irq()
1039 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2400pci_set_state()
1040 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2400pci_set_state()
1041 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2400pci_set_state()
1042 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2400pci_set_state()
1112 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); in rt2400pci_write_tx_desc()
1116 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length); in rt2400pci_write_tx_desc()
1117 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length); in rt2400pci_write_tx_desc()
1121 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); in rt2400pci_write_tx_desc()
1122 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); in rt2400pci_write_tx_desc()
1123 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); in rt2400pci_write_tx_desc()
1124 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); in rt2400pci_write_tx_desc()
1125 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); in rt2400pci_write_tx_desc()
1126 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); in rt2400pci_write_tx_desc()
1130 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, in rt2400pci_write_tx_desc()
1132 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); in rt2400pci_write_tx_desc()
1133 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); in rt2400pci_write_tx_desc()
1134 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, in rt2400pci_write_tx_desc()
1136 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); in rt2400pci_write_tx_desc()
1137 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); in rt2400pci_write_tx_desc()
1146 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); in rt2400pci_write_tx_desc()
1147 rt2x00_set_field32(&word, TXD_W0_VALID, 1); in rt2400pci_write_tx_desc()
1148 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, in rt2400pci_write_tx_desc()
1150 rt2x00_set_field32(&word, TXD_W0_ACK, in rt2400pci_write_tx_desc()
1152 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, in rt2400pci_write_tx_desc()
1154 rt2x00_set_field32(&word, TXD_W0_RTS, in rt2400pci_write_tx_desc()
1156 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); in rt2400pci_write_tx_desc()
1157 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, in rt2400pci_write_tx_desc()
1182 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_write_beacon()
1192 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1206 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1322 rt2x00_set_field32(®, irq_field, 0); in rt2400pci_enable_interrupt()
1347 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2400pci_txstatus_tasklet()
1348 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2400pci_txstatus_tasklet()
1349 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2400pci_txstatus_tasklet()
1409 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); in rt2400pci_interrupt()
1410 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); in rt2400pci_interrupt()
1411 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); in rt2400pci_interrupt()
1635 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2400pci_probe_hw()