Lines Matching defs:rtl_phy

1196 struct rtl_phy {  struct
1197 	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
1198 	struct init_gain initgain_backup;
1199 	enum io_type current_io_type;
1201 	u8 rf_mode;
1202 	u8 rf_type;
1203 	u8 current_chan_bw;
1204 	u8 set_bwmode_inprogress;
1205 	u8 sw_chnl_inprogress;
1206 	u8 sw_chnl_stage;
1207 	u8 sw_chnl_step;
1208 	u8 current_channel;
1209 	u8 h2c_box_num;
1210 	u8 set_io_inprogress;
1211 	u8 lck_inprogress;
1214 	s32 reg_e94;
1215 	s32 reg_e9c;
1216 	s32 reg_ea4;
1217 	s32 reg_eac;
1218 	s32 reg_eb4;
1219 	s32 reg_ebc;
1220 	s32 reg_ec4;
1221 	s32 reg_ecc;
1222 	u8 rfpienable;
1223 	u8 reserve_0;
1224 	u16 reserve_1;
1225 	u32 reg_c04, reg_c08, reg_874;
1226 	u32 adda_backup[16];
1227 	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1228 	u32 iqk_bb_backup[10];
1229 	bool iqk_initialized;
1231 	bool rfpath_rx_enable[MAX_RF_PATH];
1232 	u8 reg_837;
1234 	bool need_iqk;
1235 	struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1237 	bool rfpi_enable;
1238 	bool iqk_in_progress;
1240 	u8 pwrgroup_cnt;
1241 	u8 cck_high_power;
1243 	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1245 	u32 mcs_offset[MAX_PG_GROUP][16];
1246 	u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1250 	u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1253 	u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1256 	u8 default_initialgain[4];
1259 	u8 cur_cck_txpwridx;
1260 	u8 cur_ofdm24g_txpwridx;
1261 	u8 cur_bw20_txpwridx;
1262 	u8 cur_bw40_txpwridx;
1264 	char txpwr_limit_2_4g[MAX_REGULATION_NUM]
1269 	char txpwr_limit_5g[MAX_REGULATION_NUM]
1275 	u32 rfreg_chnlval[2];
1276 	bool apk_done;
1277 	u32 reg_rf3c[2];	/* pathA / pathB  */
1279 	u32 backup_rf_0x1a;/*92ee*/
1281 	u8 framesync;
1282 	u32 framesync_c34;
1284 	u8 num_total_rfpath;
1285 	struct phy_parameters hwparam_tables[MAX_TAB];
1286 	u16 rf_pathmap;
1288 	u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1289 	enum rt_polarity_ctl polarity_ctl;