Lines Matching defs:rtl_dm
1657 struct rtl_dm { struct
1659 long entry_min_undec_sm_pwdb;
1660 long undec_sm_cck;
1661 long undec_sm_pwdb; /*out dm */
1662 long entry_max_undec_sm_pwdb;
1663 s32 ofdm_pkt_cnt;
1664 bool dm_initialgain_enable;
1665 bool dynamic_txpower_enable;
1666 bool current_turbo_edca;
1667 bool is_any_nonbepkts; /*out dm */
1668 bool is_cur_rdlstate;
1669 bool txpower_trackinginit;
1670 bool disable_framebursting;
1671 bool cck_inch14;
1672 bool txpower_tracking;
1673 bool useramask;
1674 bool rfpath_rxenable[4];
1675 bool inform_fw_driverctrldm;
1676 bool current_mrc_switch;
1677 u8 txpowercount;
1678 u8 powerindex_backup[6];
1680 u8 thermalvalue_rxgain;
1681 u8 thermalvalue_iqk;
1682 u8 thermalvalue_lck;
1683 u8 thermalvalue;
1684 u8 last_dtp_lvl;
1685 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1686 u8 thermalvalue_avg_index;
1687 u8 tm_trigger;
1688 bool done_txpower;
1689 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1690 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1691 u8 dm_flag_tmp;
1692 u8 dm_type;
1693 u8 dm_rssi_sel;
1694 u8 txpower_track_control;
1695 bool interrupt_migration;
1696 bool disable_tx_int;
1697 char ofdm_index[MAX_RF_PATH];
1698 u8 default_ofdm_index;
1699 u8 default_cck_index;
1700 char cck_index;
1701 char delta_power_index[MAX_RF_PATH];
1702 char delta_power_index_last[MAX_RF_PATH];
1703 char power_index_offset[MAX_RF_PATH];
1704 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1705 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1706 char remnant_cck_idx;
1707 bool modify_txagc_flag_path_a;
1708 bool modify_txagc_flag_path_b;
1710 bool one_entry_only;
1711 struct dm_phy_dbg_info dbginfo;
1714 bool atc_status;
1715 bool large_cfo_hit;
1716 bool is_freeze;
1717 int cfo_tail[2];
1718 int cfo_ave_pre;
1719 int crystal_cap;
1720 u8 cfo_threshold;
1721 u32 packet_count;
1722 u32 packet_count_pre;
1723 u8 tx_rate;
1726 u8 swing_idx_ofdm[MAX_RF_PATH];
1727 u8 swing_idx_ofdm_cur;
1728 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1729 bool swing_flag_ofdm;
1730 u8 swing_idx_cck;
1731 u8 swing_idx_cck_cur;
1732 u8 swing_idx_cck_base;
1733 bool swing_flag_cck;
1735 char swing_diff_2g;
1736 char swing_diff_5g;
1738 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1739 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1740 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1741 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1742 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1743 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1744 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1745 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1746 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1747 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1748 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1749 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1750 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1751 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1754 bool supp_phymode_switch;
1757 struct fast_ant_training fat_table;
1759 u8 resp_tx_path;
1760 u8 path_sel;
1761 u32 patha_sum;
1762 u32 pathb_sum;
1763 u32 patha_cnt;
1764 u32 pathb_cnt;
1766 u8 pre_channel;
1767 u8 *p_channel;
1768 u8 linked_interval;
1770 u64 last_tx_ok_cnt;
1771 u64 last_rx_ok_cnt;
2855 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) macro