62 	if (bitmask != MASKDWORD) {  in rtl8723_phy_set_bb_reg()
105 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in rtl8723_phy_rf_serial_read()
109 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in rtl8723_phy_rf_serial_read()
112 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in rtl8723_phy_rf_serial_read()
115 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in rtl8723_phy_rf_serial_read()
117 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in rtl8723_phy_rf_serial_read()
156 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in rtl8723_phy_rf_serial_write()
315 					  MASKDWORD) >> 22) & 0x3FF;  in rtl8723_phy_path_a_fill_iqk_matrix()
351 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in rtl8723_save_adda_registers()
374 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);  in rtl8723_phy_reload_adda_registers()
401 			rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);  in rtl8723_phy_path_adda_on()
403 			rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);  in rtl8723_phy_path_adda_on()
408 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);  in rtl8723_phy_path_adda_on()
412 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);  in rtl8723_phy_path_adda_on()
433 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);  in rtl8723_phy_path_a_standby()
434 	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);  in rtl8723_phy_path_a_standby()
435 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in rtl8723_phy_path_a_standby()
444 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);  in rtl8723_phy_pi_mode_switch()
445 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);  in rtl8723_phy_pi_mode_switch()