Lines Matching refs:BIT
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
72 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
86 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
104 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
142 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
145 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
151 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
154 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
158 PWR_CMD_WRITE, BIT(5), BIT(5)}, \
162 PWR_CMD_WRITE, BIT(0), 0},
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
174 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
186 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
189 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
233 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
236 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
244 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
247 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
250 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
256 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
270 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
280 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
314 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
320 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
326 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
332 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
352 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
355 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
358 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
361 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
367 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \