242 		rtl_set_bbreg(hw, addr, MASKDWORD, data);  in _rtl8723be_config_bb_reg()
584 					      MASKDWORD,  in _rtl8723be_phy_config_bb_with_headerfile()
616 							      MASKDWORD,  in _rtl8723be_phy_config_bb_with_headerfile()
870 					      MASKDWORD);  in rtl8723be_phy_get_hw_reg_originalvalue()
1528 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1530 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1540 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_a_iqk()
1541 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_iqk()
1543 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_iqk()
1544 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1545 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1546 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1548 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);  in _rtl8723be_phy_path_a_iqk()
1549 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);  in _rtl8723be_phy_path_a_iqk()
1550 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_iqk()
1551 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_iqk()
1553 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl8723be_phy_path_a_iqk()
1555 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_iqk()
1558 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_iqk()
1559 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_iqk()
1564 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1567 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1568 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1569 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1601 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1604 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1613 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1616 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_a_rx_iqk()
1617 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_rx_iqk()
1620 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1621 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1622 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1623 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1625 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);  in _rtl8723be_phy_path_a_rx_iqk()
1626 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1627 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1628 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1631 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl8723be_phy_path_a_rx_iqk()
1634 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1637 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_rx_iqk()
1638 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_rx_iqk()
1643 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1646 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1647 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1648 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1672 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);  in _rtl8723be_phy_path_a_rx_iqk()
1676 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1688 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_rx_iqk()
1691 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1692 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1693 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1694 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1696 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1697 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);  in _rtl8723be_phy_path_a_rx_iqk()
1698 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1699 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1702 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);  in _rtl8723be_phy_path_a_rx_iqk()
1705 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1708 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_rx_iqk()
1709 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_rx_iqk()
1714 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1717 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1718 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1721 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1748 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1750 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);  in _rtl8723be_phy_path_b_iqk()
1758 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_b_iqk()
1759 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_iqk()
1761 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_iqk()
1762 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1763 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1764 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1766 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);  in _rtl8723be_phy_path_b_iqk()
1767 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_iqk()
1768 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_iqk()
1769 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_iqk()
1772 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl8723be_phy_path_b_iqk()
1775 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_iqk()
1778 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_iqk()
1779 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_iqk()
1784 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1787 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1788 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1789 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1821 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1823 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);  in _rtl8723be_phy_path_b_rx_iqk()
1837 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_b_rx_iqk()
1838 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_rx_iqk()
1841 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1842 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1843 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1844 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1846 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);  in _rtl8723be_phy_path_b_rx_iqk()
1847 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1848 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1849 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1852 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl8723be_phy_path_b_rx_iqk()
1854 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1857 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_rx_iqk()
1858 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_rx_iqk()
1863 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1865 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1866 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1867 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1891 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);  in _rtl8723be_phy_path_b_rx_iqk()
1896 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1908 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_rx_iqk()
1911 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1912 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1913 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1914 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1916 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1917 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);  in _rtl8723be_phy_path_b_rx_iqk()
1918 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1919 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1922 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);  in _rtl8723be_phy_path_b_rx_iqk()
1924 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1927 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_rx_iqk()
1928 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_rx_iqk()
1933 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1935 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1936 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1972 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl8723be_phy_path_b_fill_iqk_matrix()
2124 	path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);  in _rtl8723be_phy_iq_calibrate()
2130 	rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);  in _rtl8723be_phy_iq_calibrate()
2131 	rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);  in _rtl8723be_phy_iq_calibrate()
2132 	rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);  in _rtl8723be_phy_iq_calibrate()
2140 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2142 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2156 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2158 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2177 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2180 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2194 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2197 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2207 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl8723be_phy_iq_calibrate()
2218 		rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);  in _rtl8723be_phy_iq_calibrate()
2227 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);  in _rtl8723be_phy_iq_calibrate()
2228 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);  in _rtl8723be_phy_iq_calibrate()
2315 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);  in _rtl8723be_phy_set_rfpath_switch()
2317 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2);  in _rtl8723be_phy_set_rfpath_switch()
2359 	path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);  in rtl8723be_phy_iq_calibrate()
2461 	rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);  in rtl8723be_phy_iq_calibrate()