Lines Matching refs:BIT
69 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
72 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
75 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
78 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
81 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
84 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
87 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
98 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
101 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
104 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
112 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
116 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
119 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
122 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
125 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
133 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
136 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
139 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
150 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
153 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
157 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
160 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
163 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
166 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
174 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
177 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
180 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
183 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
186 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
194 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
197 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
205 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
231 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
237 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
243 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
249 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
269 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
272 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
275 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
281 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\