91 	if (bitmask != MASKDWORD) {  in rtl92ee_phy_set_bb_reg()
176 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
180 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
183 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in _rtl92ee_phy_rf_serial_read()
186 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in _rtl92ee_phy_rf_serial_read()
223 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in _rtl92ee_phy_rf_serial_write()
324 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);  in _rtl92ee_config_rf_reg()
333 							 MASKDWORD);  in _rtl92ee_config_rf_reg()
343 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);  in _rtl92ee_config_rf_reg()
355 							 MASKDWORD);  in _rtl92ee_config_rf_reg()
399 		rtl_set_bbreg(hw, addr, MASKDWORD , data);  in _rtl92ee_config_bb_reg()
762 				rtl_set_bbreg(hw, array[i], MASKDWORD,  in phy_config_bb_with_hdr_file()
792 							      MASKDWORD,  in phy_config_bb_with_hdr_file()
1063 					      ROFDM0_RXDETECTOR2, MASKDWORD);  in rtl92ee_phy_get_hw_reg_originalvalue()
1971 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_iqk()
1973 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_iqk()
1975 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_iqk()
1976 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1977 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1978 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1980 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303);  in _rtl92ee_phy_path_a_iqk()
1981 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000);  in _rtl92ee_phy_path_a_iqk()
1984 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl92ee_phy_path_a_iqk()
1987 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl92ee_phy_path_a_iqk()
1988 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_iqk()
1992 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1993 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1994 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
2012 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
2014 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
2016 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
2017 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
2019 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
2020 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
2021 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_iqk()
2022 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
2024 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2);  in _rtl92ee_phy_path_b_iqk()
2025 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000);  in _rtl92ee_phy_path_b_iqk()
2028 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl92ee_phy_path_b_iqk()
2031 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_iqk()
2032 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_iqk()
2036 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2037 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2038 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2057 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2069 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2072 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_path_a_rx_iqk()
2073 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_a_rx_iqk()
2076 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2077 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2078 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2079 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2081 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2082 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2085 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl92ee_phy_path_a_rx_iqk()
2088 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_a_rx_iqk()
2089 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_rx_iqk()
2094 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2095 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2096 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2104 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2111 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);  in _rtl92ee_phy_path_a_rx_iqk()
2114 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2127 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2130 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_a_rx_iqk()
2133 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2134 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2135 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2136 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2138 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2139 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2142 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);  in _rtl92ee_phy_path_a_rx_iqk()
2144 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_a_rx_iqk()
2145 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_rx_iqk()
2149 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2150 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2154 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2173 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2184 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2187 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_path_b_rx_iqk()
2188 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_b_rx_iqk()
2191 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2192 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2193 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2194 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2196 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2197 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2200 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl92ee_phy_path_b_rx_iqk()
2203 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_rx_iqk()
2204 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_rx_iqk()
2209 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2210 	reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2211 	reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2219 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2226 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);  in _rtl92ee_phy_path_b_rx_iqk()
2229 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2241 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2244 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_b_rx_iqk()
2247 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2248 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2249 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2250 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2252 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2253 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2256 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);  in _rtl92ee_phy_path_b_rx_iqk()
2258 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_rx_iqk()
2259 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_rx_iqk()
2263 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2264 	reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2265 	reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2268 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2293 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl92ee_phy_path_a_fill_iqk_matrix()
2338 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl92ee_phy_path_b_fill_iqk_matrix()
2378 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in _rtl92ee_phy_save_adda_registers()
2400 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);  in _rtl92ee_phy_reload_adda_registers()
2423 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616);  in _rtl92ee_phy_path_adda_on()
2425 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);  in _rtl92ee_phy_path_adda_on()
2429 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);  in _rtl92ee_phy_path_adda_on()
2440 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);  in _rtl92ee_phy_path_a_standby()
2442 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_standby()
2561 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);  in _rtl92ee_phy_iq_calibrate()
2562 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);  in _rtl92ee_phy_iq_calibrate()
2563 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);  in _rtl92ee_phy_iq_calibrate()
2574 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2575 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_iq_calibrate()
2576 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_iq_calibrate()
2586 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2589 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2606 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2610 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2628 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2629 		rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_iq_calibrate()
2630 		rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_iq_calibrate()
2639 							MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2643 							MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2659 						       MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2663 						       MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2679 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl92ee_phy_iq_calibrate()
2704 		rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);  in _rtl92ee_phy_iq_calibrate()
2705 		rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);  in _rtl92ee_phy_iq_calibrate()