273 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92d_phy_rf_serial_read()
321 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92d_phy_rf_serial_write()
415 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
417 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
419 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
422 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
425 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
427 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
429 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
431 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
435 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in _rtl92d_phy_init_bb_rf_register_definition()
437 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in _rtl92d_phy_init_bb_rf_register_definition()
441 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in _rtl92d_phy_init_bb_rf_register_definition()
443 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in _rtl92d_phy_init_bb_rf_register_definition()
447 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =  in _rtl92d_phy_init_bb_rf_register_definition()
449 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in _rtl92d_phy_init_bb_rf_register_definition()
454 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
455 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
456 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
457 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
461 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
463 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
465 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
467 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
471 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;  in _rtl92d_phy_init_bb_rf_register_definition()
473 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in _rtl92d_phy_init_bb_rf_register_definition()
477 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;  in _rtl92d_phy_init_bb_rf_register_definition()
479 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in _rtl92d_phy_init_bb_rf_register_definition()
483 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
484 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
485 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
486 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
489 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
490 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
491 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
492 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
495 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
496 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
497 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
498 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
501 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
502 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
503 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
504 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
507 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
508 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
509 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
510 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
513 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
514 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
515 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
516 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
519 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
520 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
521 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
522 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
525 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
526 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
527 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
528 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
531 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
532 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
1173 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92d_phy_enable_rf_env()
1209 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92d_phy_restore_rf_env()