Lines Matching refs:val32
1020 addr, 0, &priv->usb_buf.val32, sizeof(u32), in rtl8xxxu_read32()
1022 data = le32_to_cpu(priv->usb_buf.val32); in rtl8xxxu_read32()
1076 priv->usb_buf.val32 = cpu_to_le32(val); in rtl8xxxu_write32()
1079 addr, 0, &priv->usb_buf.val32, sizeof(u32), in rtl8xxxu_write32()
1132 u32 hssia, val32, retval; in rtl8xxxu_read_rfreg() local
1136 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); in rtl8xxxu_read_rfreg()
1138 val32 = hssia; in rtl8xxxu_read_rfreg()
1140 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; in rtl8xxxu_read_rfreg()
1141 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); in rtl8xxxu_read_rfreg()
1142 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; in rtl8xxxu_read_rfreg()
1148 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); in rtl8xxxu_read_rfreg()
1155 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); in rtl8xxxu_read_rfreg()
1156 if (val32 & FPGA0_HSSI_PARM1_PI) in rtl8xxxu_read_rfreg()
1247 u32 val32; in rtl8723a_enable_rf() local
1253 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); in rtl8723a_enable_rf()
1254 val32 &= ~(BIT(4) | BIT(5)); in rtl8723a_enable_rf()
1255 val32 |= BIT(3); in rtl8723a_enable_rf()
1257 val32 &= ~(BIT(20) | BIT(21)); in rtl8723a_enable_rf()
1258 val32 |= BIT(19); in rtl8723a_enable_rf()
1260 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); in rtl8723a_enable_rf()
1262 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8723a_enable_rf()
1263 val32 &= ~OFDM_RF_PATH_TX_MASK; in rtl8723a_enable_rf()
1265 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; in rtl8723a_enable_rf()
1267 val32 |= OFDM_RF_PATH_TX_B; in rtl8723a_enable_rf()
1269 val32 |= OFDM_RF_PATH_TX_A; in rtl8723a_enable_rf()
1270 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8723a_enable_rf()
1272 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8723a_enable_rf()
1273 val32 &= ~FPGA_RF_MODE_JAPAN; in rtl8723a_enable_rf()
1274 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723a_enable_rf()
1291 u32 val32; in rtl8723a_disable_rf() local
1298 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); in rtl8723a_disable_rf()
1299 val32 &= ~(BIT(3) | BIT(4) | BIT(5)); in rtl8723a_disable_rf()
1301 val32 &= ~(BIT(19) | BIT(20) | BIT(21)); in rtl8723a_disable_rf()
1302 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); in rtl8723a_disable_rf()
1305 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8723a_disable_rf()
1306 val32 &= ~OFDM_RF_PATH_TX_MASK; in rtl8723a_disable_rf()
1307 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8723a_disable_rf()
1310 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8723a_disable_rf()
1311 val32 |= FPGA_RF_MODE_JAPAN; in rtl8723a_disable_rf()
1312 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723a_disable_rf()
1371 u32 val32, rsr; in rtl8723au_config_channel() local
1388 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8723au_config_channel()
1389 val32 &= ~FPGA_RF_MODE; in rtl8723au_config_channel()
1390 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723au_config_channel()
1392 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8723au_config_channel()
1393 val32 &= ~FPGA_RF_MODE; in rtl8723au_config_channel()
1394 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8723au_config_channel()
1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); in rtl8723au_config_channel()
1397 val32 |= FPGA0_ANALOG2_20MHZ; in rtl8723au_config_channel()
1398 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); in rtl8723au_config_channel()
1419 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8723au_config_channel()
1420 val32 |= FPGA_RF_MODE; in rtl8723au_config_channel()
1421 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8723au_config_channel()
1423 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8723au_config_channel()
1424 val32 |= FPGA_RF_MODE; in rtl8723au_config_channel()
1425 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8723au_config_channel()
1431 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); in rtl8723au_config_channel()
1432 val32 &= ~CCK0_SIDEBAND; in rtl8723au_config_channel()
1434 val32 |= CCK0_SIDEBAND; in rtl8723au_config_channel()
1435 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8723au_config_channel()
1437 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); in rtl8723au_config_channel()
1438 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ in rtl8723au_config_channel()
1440 val32 |= OFDM_LSTF_PRIME_CH_LOW; in rtl8723au_config_channel()
1442 val32 |= OFDM_LSTF_PRIME_CH_HIGH; in rtl8723au_config_channel()
1443 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8723au_config_channel()
1445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); in rtl8723au_config_channel()
1446 val32 &= ~FPGA0_ANALOG2_20MHZ; in rtl8723au_config_channel()
1447 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); in rtl8723au_config_channel()
1449 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); in rtl8723au_config_channel()
1450 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); in rtl8723au_config_channel()
1452 val32 |= FPGA0_PS_UPPER_CHANNEL; in rtl8723au_config_channel()
1454 val32 |= FPGA0_PS_LOWER_CHANNEL; in rtl8723au_config_channel()
1455 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); in rtl8723au_config_channel()
1463 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); in rtl8723au_config_channel()
1464 val32 &= ~MODE_AG_CHANNEL_MASK; in rtl8723au_config_channel()
1465 val32 |= channel; in rtl8723au_config_channel()
1466 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); in rtl8723au_config_channel()
1481 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); in rtl8723au_config_channel()
1483 val32 &= ~MODE_AG_CHANNEL_20MHZ; in rtl8723au_config_channel()
1485 val32 |= MODE_AG_CHANNEL_20MHZ; in rtl8723au_config_channel()
1486 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); in rtl8723au_config_channel()
1495 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; in rtl8723a_set_tx_power() local
1537 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723a_set_tx_power()
1538 val32 &= 0xffff00ff; in rtl8723a_set_tx_power()
1539 val32 |= (cck[0] << 8); in rtl8723a_set_tx_power()
1540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723a_set_tx_power()
1542 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723a_set_tx_power()
1543 val32 &= 0xff; in rtl8723a_set_tx_power()
1544 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); in rtl8723a_set_tx_power()
1545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723a_set_tx_power()
1547 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723a_set_tx_power()
1548 val32 &= 0xffffff00; in rtl8723a_set_tx_power()
1549 val32 |= cck[1]; in rtl8723a_set_tx_power()
1550 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723a_set_tx_power()
1552 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8723a_set_tx_power()
1553 val32 &= 0xff; in rtl8723a_set_tx_power()
1554 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); in rtl8723a_set_tx_power()
1555 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8723a_set_tx_power()
1682 u32 val32, bonding; in rtl8xxxu_identify_chip() local
1685 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8xxxu_identify_chip()
1686 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> in rtl8xxxu_identify_chip()
1688 if (val32 & SYS_CFG_TRP_VAUX_EN) { in rtl8xxxu_identify_chip()
1693 if (val32 & SYS_CFG_BT_FUNC) { in rtl8xxxu_identify_chip()
1700 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8xxxu_identify_chip()
1701 if (val32 & MULTI_WIFI_FUNC_EN) in rtl8xxxu_identify_chip()
1703 if (val32 & MULTI_BT_FUNC_EN) in rtl8xxxu_identify_chip()
1705 if (val32 & MULTI_GPS_FUNC_EN) in rtl8xxxu_identify_chip()
1707 } else if (val32 & SYS_CFG_TYPE_ID) { in rtl8xxxu_identify_chip()
1733 if (val32 & SYS_CFG_VENDOR_ID) in rtl8xxxu_identify_chip()
1736 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8xxxu_identify_chip()
1737 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; in rtl8xxxu_identify_chip()
1897 u32 val32; in rtl8xxxu_read_efuse8() local
1910 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); in rtl8xxxu_read_efuse8()
1912 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); in rtl8xxxu_read_efuse8()
1913 if (val32 & BIT(31)) in rtl8xxxu_read_efuse8()
1921 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); in rtl8xxxu_read_efuse8()
1923 *data = val32 & 0xff; in rtl8xxxu_read_efuse8()
1933 u32 val32; in rtl8xxxu_read_efuse() local
1941 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); in rtl8xxxu_read_efuse()
1942 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; in rtl8xxxu_read_efuse()
1943 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); in rtl8xxxu_read_efuse()
2050 u32 val32; in rtl8xxxu_start_firmware() local
2054 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); in rtl8xxxu_start_firmware()
2055 if (val32 & MCU_FW_DL_CSUM_REPORT) in rtl8xxxu_start_firmware()
2065 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); in rtl8xxxu_start_firmware()
2066 val32 |= MCU_FW_DL_READY; in rtl8xxxu_start_firmware()
2067 val32 &= ~MCU_WINT_INIT_READY; in rtl8xxxu_start_firmware()
2068 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); in rtl8xxxu_start_firmware()
2072 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); in rtl8xxxu_start_firmware()
2073 if (val32 & MCU_WINT_INIT_READY) in rtl8xxxu_start_firmware()
2094 u32 val32; in rtl8xxxu_download_firmware() local
2110 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); in rtl8xxxu_download_firmware()
2111 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32 & ~BIT(19)); in rtl8xxxu_download_firmware()
2331 u32 val32; in rtl8xxxu_init_phy_bb() local
2352 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8xxxu_init_phy_bb()
2353 val32 &= ~AFE_XTAL_RF_GATE; in rtl8xxxu_init_phy_bb()
2355 val32 &= ~AFE_XTAL_BT_GATE; in rtl8xxxu_init_phy_bb()
2356 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8xxxu_init_phy_bb()
2380 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); in rtl8xxxu_init_phy_bb()
2381 val32 &= ~(BIT(0) | BIT(1)); in rtl8xxxu_init_phy_bb()
2382 val32 |= BIT(1); in rtl8xxxu_init_phy_bb()
2383 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); in rtl8xxxu_init_phy_bb()
2385 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); in rtl8xxxu_init_phy_bb()
2386 val32 &= ~0x300033; in rtl8xxxu_init_phy_bb()
2387 val32 |= 0x200022; in rtl8xxxu_init_phy_bb()
2388 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); in rtl8xxxu_init_phy_bb()
2390 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8xxxu_init_phy_bb()
2391 val32 &= 0xff000000; in rtl8xxxu_init_phy_bb()
2392 val32 |= 0x45000000; in rtl8xxxu_init_phy_bb()
2393 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8xxxu_init_phy_bb()
2395 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8xxxu_init_phy_bb()
2396 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); in rtl8xxxu_init_phy_bb()
2397 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | in rtl8xxxu_init_phy_bb()
2399 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8xxxu_init_phy_bb()
2401 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); in rtl8xxxu_init_phy_bb()
2402 val32 &= ~(BIT(4) | BIT(5)); in rtl8xxxu_init_phy_bb()
2403 val32 |= BIT(4); in rtl8xxxu_init_phy_bb()
2404 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); in rtl8xxxu_init_phy_bb()
2406 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); in rtl8xxxu_init_phy_bb()
2407 val32 &= ~(BIT(27) | BIT(26)); in rtl8xxxu_init_phy_bb()
2408 val32 |= BIT(27); in rtl8xxxu_init_phy_bb()
2409 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); in rtl8xxxu_init_phy_bb()
2411 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); in rtl8xxxu_init_phy_bb()
2412 val32 &= ~(BIT(27) | BIT(26)); in rtl8xxxu_init_phy_bb()
2413 val32 |= BIT(27); in rtl8xxxu_init_phy_bb()
2414 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); in rtl8xxxu_init_phy_bb()
2416 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); in rtl8xxxu_init_phy_bb()
2417 val32 &= ~(BIT(27) | BIT(26)); in rtl8xxxu_init_phy_bb()
2418 val32 |= BIT(27); in rtl8xxxu_init_phy_bb()
2419 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); in rtl8xxxu_init_phy_bb()
2421 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); in rtl8xxxu_init_phy_bb()
2422 val32 &= ~(BIT(27) | BIT(26)); in rtl8xxxu_init_phy_bb()
2423 val32 |= BIT(27); in rtl8xxxu_init_phy_bb()
2424 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); in rtl8xxxu_init_phy_bb()
2426 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); in rtl8xxxu_init_phy_bb()
2427 val32 &= ~(BIT(27) | BIT(26)); in rtl8xxxu_init_phy_bb()
2428 val32 |= BIT(27); in rtl8xxxu_init_phy_bb()
2429 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); in rtl8xxxu_init_phy_bb()
2439 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); in rtl8xxxu_init_phy_bb()
2442 val32 &= 0xff000fff; in rtl8xxxu_init_phy_bb()
2443 val32 |= ((val8 | (val8 << 6)) << 12); in rtl8xxxu_init_phy_bb()
2445 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); in rtl8xxxu_init_phy_bb()
2452 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; in rtl8xxxu_init_phy_bb()
2454 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); in rtl8xxxu_init_phy_bb()
2513 u32 val32; in rtl8xxxu_init_phy_rf() local
2540 val32 = rtl8xxxu_read32(priv, reg_int_oe); in rtl8xxxu_init_phy_rf()
2541 val32 |= BIT(20); /* 0x10 << 16 */ in rtl8xxxu_init_phy_rf()
2542 rtl8xxxu_write32(priv, reg_int_oe, val32); in rtl8xxxu_init_phy_rf()
2545 val32 = rtl8xxxu_read32(priv, reg_int_oe); in rtl8xxxu_init_phy_rf()
2546 val32 |= BIT(4); in rtl8xxxu_init_phy_rf()
2547 rtl8xxxu_write32(priv, reg_int_oe, val32); in rtl8xxxu_init_phy_rf()
2553 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); in rtl8xxxu_init_phy_rf()
2554 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; in rtl8xxxu_init_phy_rf()
2555 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); in rtl8xxxu_init_phy_rf()
2558 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); in rtl8xxxu_init_phy_rf()
2559 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; in rtl8xxxu_init_phy_rf()
2560 rtl8xxxu_write32(priv, reg_hssi_parm2, val32); in rtl8xxxu_init_phy_rf()
2751 u32 val32; in rtl8xxxu_fill_iqk_matrix_a() local
2756 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_a()
2757 oldval = val32 >> 22; in rtl8xxxu_fill_iqk_matrix_a()
2764 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_a()
2765 val32 &= ~0x3ff; in rtl8xxxu_fill_iqk_matrix_a()
2766 val32 |= tx0_a; in rtl8xxxu_fill_iqk_matrix_a()
2767 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2769 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); in rtl8xxxu_fill_iqk_matrix_a()
2770 val32 &= ~BIT(31); in rtl8xxxu_fill_iqk_matrix_a()
2772 val32 |= BIT(31); in rtl8xxxu_fill_iqk_matrix_a()
2773 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_a()
2780 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); in rtl8xxxu_fill_iqk_matrix_a()
2781 val32 &= ~0xf0000000; in rtl8xxxu_fill_iqk_matrix_a()
2782 val32 |= (((tx0_c & 0x3c0) >> 6) << 28); in rtl8xxxu_fill_iqk_matrix_a()
2783 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2785 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_a()
2786 val32 &= ~0x003f0000; in rtl8xxxu_fill_iqk_matrix_a()
2787 val32 |= ((tx0_c & 0x3f) << 16); in rtl8xxxu_fill_iqk_matrix_a()
2788 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2790 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); in rtl8xxxu_fill_iqk_matrix_a()
2791 val32 &= ~BIT(29); in rtl8xxxu_fill_iqk_matrix_a()
2793 val32 |= BIT(29); in rtl8xxxu_fill_iqk_matrix_a()
2794 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_a()
2803 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_a()
2804 val32 &= ~0x3ff; in rtl8xxxu_fill_iqk_matrix_a()
2805 val32 |= (reg & 0x3ff); in rtl8xxxu_fill_iqk_matrix_a()
2806 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2810 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_a()
2811 val32 &= ~0xfc00; in rtl8xxxu_fill_iqk_matrix_a()
2812 val32 |= ((reg << 10) & 0xfc00); in rtl8xxxu_fill_iqk_matrix_a()
2813 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_a()
2817 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); in rtl8xxxu_fill_iqk_matrix_a()
2818 val32 &= ~0xf0000000; in rtl8xxxu_fill_iqk_matrix_a()
2819 val32 |= (reg << 28); in rtl8xxxu_fill_iqk_matrix_a()
2820 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); in rtl8xxxu_fill_iqk_matrix_a()
2829 u32 val32; in rtl8xxxu_fill_iqk_matrix_b() local
2834 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_b()
2835 oldval = val32 >> 22; in rtl8xxxu_fill_iqk_matrix_b()
2842 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_b()
2843 val32 &= ~0x3ff; in rtl8xxxu_fill_iqk_matrix_b()
2844 val32 |= tx1_a; in rtl8xxxu_fill_iqk_matrix_b()
2845 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2847 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); in rtl8xxxu_fill_iqk_matrix_b()
2848 val32 &= ~BIT(27); in rtl8xxxu_fill_iqk_matrix_b()
2850 val32 |= BIT(27); in rtl8xxxu_fill_iqk_matrix_b()
2851 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_b()
2858 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); in rtl8xxxu_fill_iqk_matrix_b()
2859 val32 &= ~0xf0000000; in rtl8xxxu_fill_iqk_matrix_b()
2860 val32 |= (((tx1_c & 0x3c0) >> 6) << 28); in rtl8xxxu_fill_iqk_matrix_b()
2861 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2863 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_b()
2864 val32 &= ~0x003f0000; in rtl8xxxu_fill_iqk_matrix_b()
2865 val32 |= ((tx1_c & 0x3f) << 16); in rtl8xxxu_fill_iqk_matrix_b()
2866 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2868 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); in rtl8xxxu_fill_iqk_matrix_b()
2869 val32 &= ~BIT(25); in rtl8xxxu_fill_iqk_matrix_b()
2871 val32 |= BIT(25); in rtl8xxxu_fill_iqk_matrix_b()
2872 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); in rtl8xxxu_fill_iqk_matrix_b()
2881 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_b()
2882 val32 &= ~0x3ff; in rtl8xxxu_fill_iqk_matrix_b()
2883 val32 |= (reg & 0x3ff); in rtl8xxxu_fill_iqk_matrix_b()
2884 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2888 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); in rtl8xxxu_fill_iqk_matrix_b()
2889 val32 &= ~0xfc00; in rtl8xxxu_fill_iqk_matrix_b()
2890 val32 |= ((reg << 10) & 0xfc00); in rtl8xxxu_fill_iqk_matrix_b()
2891 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); in rtl8xxxu_fill_iqk_matrix_b()
2895 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); in rtl8xxxu_fill_iqk_matrix_b()
2896 val32 &= ~0x0000f000; in rtl8xxxu_fill_iqk_matrix_b()
2897 val32 |= (reg << 12); in rtl8xxxu_fill_iqk_matrix_b()
2898 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); in rtl8xxxu_fill_iqk_matrix_b()
3031 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; in rtl8xxxu_iqk_path_a() local
3039 val32 = (priv->rf_paths > 1) ? 0x28160202 : in rtl8xxxu_iqk_path_a()
3042 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); in rtl8xxxu_iqk_path_a()
3126 u32 i, val32; in rtl8xxxu_phy_iqcalibrate() local
3167 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); in rtl8xxxu_phy_iqcalibrate()
3168 if (val32 & FPGA0_HSSI_PARM1_PI) in rtl8xxxu_phy_iqcalibrate()
3178 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_phy_iqcalibrate()
3179 val32 &= ~FPGA_RF_MODE_CCK; in rtl8xxxu_phy_iqcalibrate()
3180 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_phy_iqcalibrate()
3186 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8xxxu_phy_iqcalibrate()
3187 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); in rtl8xxxu_phy_iqcalibrate()
3188 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8xxxu_phy_iqcalibrate()
3190 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8xxxu_phy_iqcalibrate()
3191 val32 &= ~BIT(10); in rtl8xxxu_phy_iqcalibrate()
3192 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8xxxu_phy_iqcalibrate()
3193 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8xxxu_phy_iqcalibrate()
3194 val32 &= ~BIT(10); in rtl8xxxu_phy_iqcalibrate()
3195 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8xxxu_phy_iqcalibrate()
3219 val32 = rtl8xxxu_read32(priv, in rtl8xxxu_phy_iqcalibrate()
3221 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3222 val32 = rtl8xxxu_read32(priv, in rtl8xxxu_phy_iqcalibrate()
3224 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3225 val32 = rtl8xxxu_read32(priv, in rtl8xxxu_phy_iqcalibrate()
3227 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3228 val32 = rtl8xxxu_read32(priv, in rtl8xxxu_phy_iqcalibrate()
3230 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3237 val32 = rtl8xxxu_read32(priv, in rtl8xxxu_phy_iqcalibrate()
3239 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3240 val32 = rtl8xxxu_read32(priv, in rtl8xxxu_phy_iqcalibrate()
3242 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3263 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8xxxu_phy_iqcalibrate()
3264 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3265 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8xxxu_phy_iqcalibrate()
3266 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3267 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8xxxu_phy_iqcalibrate()
3268 result[t][6] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3269 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8xxxu_phy_iqcalibrate()
3270 result[t][7] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3274 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8xxxu_phy_iqcalibrate()
3275 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3276 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8xxxu_phy_iqcalibrate()
3277 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8xxxu_phy_iqcalibrate()
3294 val32 = 0x01000000; in rtl8xxxu_phy_iqcalibrate()
3295 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); in rtl8xxxu_phy_iqcalibrate()
3296 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); in rtl8xxxu_phy_iqcalibrate()
3426 u32 val32; in rtl8723a_phy_lc_calibrate() local
3434 val32 = lstf & ~OFDM_LSTF_MASK; in rtl8723a_phy_lc_calibrate()
3435 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8723a_phy_lc_calibrate()
3459 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8723a_phy_lc_calibrate()
3460 val32 |= 0x08000; in rtl8723a_phy_lc_calibrate()
3461 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8723a_phy_lc_calibrate()
3590 u8 val32; in rtl8xxxu_active_to_lps() local
3599 val32 = rtl8xxxu_read32(priv, 0x5f8); in rtl8xxxu_active_to_lps()
3600 if (!val32) in rtl8xxxu_active_to_lps()
3666 u32 val32; in rtl8xxxu_emu_to_active() local
3693 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8xxxu_emu_to_active()
3694 if (val32 & BIT(17)) in rtl8xxxu_emu_to_active()
3723 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8xxxu_emu_to_active()
3724 val32 |= APS_FSMCO_MAC_ENABLE; in rtl8xxxu_emu_to_active()
3725 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8xxxu_emu_to_active()
3728 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8xxxu_emu_to_active()
3729 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8xxxu_emu_to_active()
3784 u32 val32; in rtl8723au_power_on() local
3818 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); in rtl8723au_power_on()
3819 val32 &= ~(BIT(28) | BIT(29) | BIT(30)); in rtl8723au_power_on()
3820 val32 |= (0x06 << 28); in rtl8723au_power_on()
3821 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); in rtl8723au_power_on()
3832 u32 val32; in rtl8192cu_power_on() local
3924 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); in rtl8192cu_power_on()
3925 val32 &= ~BIT(1); in rtl8192cu_power_on()
3926 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); in rtl8192cu_power_on()
3937 u32 val32; in rtl8xxxu_power_off() local
3943 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); in rtl8xxxu_power_off()
3944 val32 |= BIT(1); in rtl8xxxu_power_off()
3945 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); in rtl8xxxu_power_off()
3996 u32 val32; in rtl8xxxu_init_device() local
4084 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | in rtl8xxxu_init_device()
4088 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8xxxu_init_device()
4104 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD; in rtl8xxxu_init_device()
4107 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT); in rtl8xxxu_init_device()
4109 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT); in rtl8xxxu_init_device()
4111 rtl8xxxu_write32(priv, REG_RQPN, val32); in rtl8xxxu_init_device()
4157 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | in rtl8xxxu_init_device()
4161 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_init_device()
4172 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); in rtl8xxxu_init_device()
4173 val32 &= ~RESPONSE_RATE_BITMAP_ALL; in rtl8xxxu_init_device()
4174 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; in rtl8xxxu_init_device()
4175 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8xxxu_init_device()
4225 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_init_device()
4226 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); in rtl8xxxu_init_device()
4227 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_init_device()
4301 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); in rtl8xxxu_init_device()
4302 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR) in rtl8xxxu_init_device()
4305 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8xxxu_init_device()
4306 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK; in rtl8xxxu_init_device()
4308 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8xxxu_init_device()
4309 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK; in rtl8xxxu_init_device()
4319 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_init_device()
4320 if ((val32 & 0xff000000) != 0x83000000) { in rtl8xxxu_init_device()
4321 val32 |= FPGA_RF_MODE_CCK; in rtl8xxxu_init_device()
4322 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_init_device()
4325 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); in rtl8xxxu_init_device()
4326 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; in rtl8xxxu_init_device()
4328 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); in rtl8xxxu_init_device()
4344 u32 cmd, val32, addr, ctrl; in rtl8xxxu_cam_write() local
4361 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); in rtl8xxxu_cam_write()
4364 val32 = mac[2] | (mac[3] << 8) | in rtl8xxxu_cam_write()
4369 val32 = key->key[i] | (key->key[i + 1] << 8) | in rtl8xxxu_cam_write()
4374 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); in rtl8xxxu_cam_write()
4425 u32 val32; in rtl8xxxu_set_basic_rates() local
4430 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); in rtl8xxxu_set_basic_rates()
4431 val32 &= ~RESPONSE_RATE_BITMAP_ALL; in rtl8xxxu_set_basic_rates()
4432 val32 |= rate_cfg; in rtl8xxxu_set_basic_rates()
4433 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8xxxu_set_basic_rates()
4451 u32 val32; in rtl8xxxu_bss_info_changed() local
4491 val32 = rtl8xxxu_read32(priv, REG_RCR); in rtl8xxxu_bss_info_changed()
4492 val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON; in rtl8xxxu_bss_info_changed()
4493 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_bss_info_changed()
4508 val32 = rtl8xxxu_read32(priv, REG_RCR); in rtl8xxxu_bss_info_changed()
4509 val32 &= ~(RCR_CHECK_BSSID_MATCH | in rtl8xxxu_bss_info_changed()
4511 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_bss_info_changed()
4528 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); in rtl8xxxu_bss_info_changed()
4530 val32 |= RSR_ACK_SHORT_PREAMBLE; in rtl8xxxu_bss_info_changed()
4532 val32 &= ~RSR_ACK_SHORT_PREAMBLE; in rtl8xxxu_bss_info_changed()
4533 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8xxxu_bss_info_changed()
4833 u32 ampdu, val32; in rtl8xxxu_tx() local
4836 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; in rtl8xxxu_tx()
4837 tx_desc->txdw2 |= cpu_to_le32(val32); in rtl8xxxu_tx()
5124 u32 val32; in rtl8xxxu_submit_int_urb() local
5141 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); in rtl8xxxu_submit_int_urb()
5142 val32 |= USB_HIMR_CPWM; in rtl8xxxu_submit_int_urb()
5143 rtl8xxxu_write32(priv, REG_USB_HIMR, val32); in rtl8xxxu_submit_int_urb()
5236 u32 val32; in rtl8xxxu_conf_tx() local
5241 val32 = aifs | in rtl8xxxu_conf_tx()
5249 __func__, queue, val32, param->acm, acm_ctrl); in rtl8xxxu_conf_tx()
5254 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); in rtl8xxxu_conf_tx()
5258 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); in rtl8xxxu_conf_tx()
5262 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); in rtl8xxxu_conf_tx()
5266 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); in rtl8xxxu_conf_tx()
5312 u32 val32; in rtl8xxxu_set_key() local
5364 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | in rtl8xxxu_set_key()
5366 rtl8xxxu_write32(priv, REG_CAM_CMD, val32); in rtl8xxxu_set_key()