Lines Matching refs:GENMASK
20 #ifndef GENMASK
21 #define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) macro
34 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
35 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
36 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
37 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
38 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
64 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
65 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
66 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
75 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
78 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
86 #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
100 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
101 #define MT_INT_TX_DONE_ALL GENMASK(13, 4)
120 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
123 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
132 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
136 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
140 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
146 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
152 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
153 #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
161 #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 27)
169 #define MT_US_CYC_CNT GENMASK(7, 0)
200 #define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
201 #define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
202 #define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)
213 #define MT_RF_CTRL_ADDR GENMASK(11, 0)
231 #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
232 #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
233 #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)
257 #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)
261 #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
262 #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
263 #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
267 #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
270 #define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)
273 #define MT_BBP_CSR_CFG_VAL GENMASK(7, 0)
274 #define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8)
295 #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
299 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
300 #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
301 #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
302 #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
306 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
307 #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
310 #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
312 #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
315 #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)
321 #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
322 #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)
347 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
348 #define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
349 #define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
350 #define MT_EDCA_CFG_CWMAX GENMASK(19, 16)
375 #define MT_TXOP_TRUN_EN GENMASK(5, 0)
376 #define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
380 #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
381 #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
399 #define MT_PROT_RATE GENMASK(15, 0)
415 #define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)
426 #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
427 #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
437 #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
438 #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
439 #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
440 #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)
443 #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
446 #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
489 #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
490 #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
491 #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
492 #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
493 #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
494 #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)
521 #define MT_TX_STAT_FIFO_PID_TYPE GENMASK(4, 1)
525 #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
526 #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
541 #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
560 #define MT_BBP_CORE_R1_BW GENMASK(4, 3)
562 #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
563 #define MT_BBP_AGC_R0_BW GENMASK(14, 12)
566 #define MT_BBP_AGC_LNA_GAIN GENMASK(21, 16)
569 #define MT_BBP_AGC_GAIN GENMASK(14, 8)
571 #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
572 #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
574 #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
591 #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
592 #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
593 #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
597 #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)
616 #define MT_SKEY_MODE_MASK GENMASK(3, 0)
622 #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)