44 	mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_DATA, value) |  in mt7601u_rf_wr()
77 	mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) |  in mt7601u_rf_rr()
141 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_wr()
165 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_rr()
435 	mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |  in __mt7601u_phy_set_channel()
507 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
508 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);  in mt7601u_read_bootup_temp()
509 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);  in mt7601u_read_bootup_temp()
528 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
529 	mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);  in mt7601u_read_bootup_temp()
530 	mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);  in mt7601u_read_bootup_temp()
566 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);  in mt7601u_rxdc_cal()
583 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_rxdc_cal()
590 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_rxdc_cal()
651 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);  in mt7601u_tssi_dc_gain_cal()
652 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);  in mt7601u_tssi_dc_gain_cal()
653 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_tssi_dc_gain_cal()
715 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_tssi_dc_gain_cal()
716 	mt7601u_wr(dev, MT_RF_SETTING_0, 0);  in mt7601u_tssi_dc_gain_cal()
945 	mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);  in mt7601u_tssi_cal()
1166 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_init_cal()
1188 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);  in mt7601u_bbp_set_bw()
1194 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);  in mt7601u_bbp_set_bw()