24 static void mt7601u_agc_reset(struct mt7601u_dev *dev);
27 mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value)  in mt7601u_rf_wr()  argument
31 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||  in mt7601u_rf_wr()
34 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_rf_wr()
37 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_rf_wr()
39 	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) {  in mt7601u_rf_wr()
44 	mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_DATA, value) |  in mt7601u_rf_wr()
49 	trace_rf_write(dev, bank, offset, value);  in mt7601u_rf_wr()
51 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_rf_wr()
54 		dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n",  in mt7601u_rf_wr()
61 mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset)  in mt7601u_rf_rr()  argument
66 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||  in mt7601u_rf_rr()
69 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_rf_rr()
72 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_rf_rr()
74 	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))  in mt7601u_rf_rr()
77 	mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) |  in mt7601u_rf_rr()
81 	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))  in mt7601u_rf_rr()
84 	val = mt7601u_rr(dev, MT_RF_CSR_CFG);  in mt7601u_rf_rr()
88 		trace_rf_read(dev, bank, offset, ret);  in mt7601u_rf_rr()
91 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_rf_rr()
94 		dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n",  in mt7601u_rf_rr()
101 mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val)  in mt7601u_rf_rmw()  argument
105 	ret = mt7601u_rf_rr(dev, bank, offset);  in mt7601u_rf_rmw()
109 	ret = mt7601u_rf_wr(dev, bank, offset, val);  in mt7601u_rf_rmw()
117 mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val)  in mt7601u_rf_set()  argument
119 	return mt7601u_rf_rmw(dev, bank, offset, 0, val);  in mt7601u_rf_set()
123 mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask)  in mt7601u_rf_clear()  argument
125 	return mt7601u_rf_rmw(dev, bank, offset, mask, 0);  in mt7601u_rf_clear()
128 static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val)  in mt7601u_bbp_wr()  argument
130 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||  in mt7601u_bbp_wr()
131 	    test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_bbp_wr()
134 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_bbp_wr()
136 	if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) {  in mt7601u_bbp_wr()
137 		dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset);  in mt7601u_bbp_wr()
141 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_wr()
145 	trace_bbp_write(dev, offset, val);  in mt7601u_bbp_wr()
147 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_bbp_wr()
150 static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset)  in mt7601u_bbp_rr()  argument
155 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)))  in mt7601u_bbp_rr()
157 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_bbp_rr()
160 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_bbp_rr()
162 	if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))  in mt7601u_bbp_rr()
165 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_rr()
170 	if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))  in mt7601u_bbp_rr()
173 	val = mt7601u_rr(dev, MT_BBP_CSR_CFG);  in mt7601u_bbp_rr()
176 		trace_bbp_read(dev, offset, ret);  in mt7601u_bbp_rr()
179 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_bbp_rr()
182 		dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n",  in mt7601u_bbp_rr()
188 static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)  in mt7601u_bbp_rmw()  argument
192 	ret = mt7601u_bbp_rr(dev, offset);  in mt7601u_bbp_rmw()
196 	mt7601u_bbp_wr(dev, offset, val);  in mt7601u_bbp_rmw()
201 static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)  in mt7601u_bbp_rmc()  argument
205 	ret = mt7601u_bbp_rr(dev, offset);  in mt7601u_bbp_rmc()
210 		mt7601u_bbp_wr(dev, offset, val);  in mt7601u_bbp_rmc()
215 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev)  in mt7601u_wait_bbp_ready()  argument
221 		val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION);  in mt7601u_wait_bbp_ready()
227 		dev_err(dev->dev, "Error: BBP is not ready\n");  in mt7601u_wait_bbp_ready()
234 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below)  in mt7601u_bbp_set_ctrlch()  argument
236 	return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0);  in mt7601u_bbp_set_ctrlch()
239 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,  in mt7601u_phy_get_rssi()  argument
263 	val -= dev->ee->lna_gain;  in mt7601u_phy_get_rssi()
264 	val -= dev->ee->rssi_offset[0];  in mt7601u_phy_get_rssi()
269 static void mt7601u_vco_cal(struct mt7601u_dev *dev)  in mt7601u_vco_cal()  argument
271 	mt7601u_rf_wr(dev, 0, 4, 0x0a);  in mt7601u_vco_cal()
272 	mt7601u_rf_wr(dev, 0, 5, 0x20);  in mt7601u_vco_cal()
273 	mt7601u_rf_set(dev, 0, 4, BIT(7));  in mt7601u_vco_cal()
277 static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal)  in mt7601u_set_bw_filter()  argument
284 	if (dev->bw != MT_BW_20)  in mt7601u_set_bw_filter()
288 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1);  in mt7601u_set_bw_filter()
292 	return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter);  in mt7601u_set_bw_filter()
295 static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev)  in mt7601u_load_bbp_temp_table_bw()  argument
299 	if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW))  in mt7601u_load_bbp_temp_table_bw()
302 	t = &bbp_mode_table[dev->temp_mode][dev->bw];  in mt7601u_load_bbp_temp_table_bw()
304 	return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n);  in mt7601u_load_bbp_temp_table_bw()
307 static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name)  in mt7601u_bbp_temp()  argument
312 	if (dev->temp_mode == mode)  in mt7601u_bbp_temp()
315 	dev->temp_mode = mode;  in mt7601u_bbp_temp()
316 	trace_temp_mode(dev, mode);  in mt7601u_bbp_temp()
318 	t = bbp_mode_table[dev->temp_mode];  in mt7601u_bbp_temp()
319 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_bbp_temp()
324 	return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_bbp_temp()
325 				       t[dev->bw].regs, t[dev->bw].n);  in mt7601u_bbp_temp()
328 static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan)  in mt7601u_apply_ch14_fixup()  argument
330 	struct mt7601u_rate_power *t = &dev->ee->power_rate_table;  in mt7601u_apply_ch14_fixup()
332 	if (hw_chan != 14 || dev->bw != MT_BW_20) {  in mt7601u_apply_ch14_fixup()
333 		mt7601u_bbp_rmw(dev, 4, 0x20, 0);  in mt7601u_apply_ch14_fixup()
334 		mt7601u_bbp_wr(dev, 178, 0xff);  in mt7601u_apply_ch14_fixup()
336 		t->cck[0].bw20 = dev->ee->real_cck_bw20[0];  in mt7601u_apply_ch14_fixup()
337 		t->cck[1].bw20 = dev->ee->real_cck_bw20[1];  in mt7601u_apply_ch14_fixup()
339 		mt7601u_bbp_wr(dev, 4, 0x60);  in mt7601u_apply_ch14_fixup()
340 		mt7601u_bbp_wr(dev, 178, 0);  in mt7601u_apply_ch14_fixup()
343 		t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2;  in mt7601u_apply_ch14_fixup()
344 		t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2;  in mt7601u_apply_ch14_fixup()
348 static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev,  in __mt7601u_phy_set_channel()  argument
372 		{ 62, 0x37 - dev->ee->lna_gain },  in __mt7601u_phy_set_channel()
373 		{ 63, 0x37 - dev->ee->lna_gain },  in __mt7601u_phy_set_channel()
374 		{ 64, 0x37 - dev->ee->lna_gain },  in __mt7601u_phy_set_channel()
380 	struct mt7601u_rate_power *t = &dev->ee->power_rate_table;  in __mt7601u_phy_set_channel()
398 			dev_err(dev->dev, "Error: invalid 40MHz channel!!\n");  in __mt7601u_phy_set_channel()
401 	if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) {  in __mt7601u_phy_set_channel()
402 		dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n",  in __mt7601u_phy_set_channel()
405 		mt7601u_bbp_set_bw(dev, bw);  in __mt7601u_phy_set_channel()
407 		mt7601u_bbp_set_ctrlch(dev, chan_ext_below);  in __mt7601u_phy_set_channel()
408 		mt7601u_mac_set_ctrlch(dev, chan_ext_below);  in __mt7601u_phy_set_channel()
409 		dev->chan_ext_below = chan_ext_below;  in __mt7601u_phy_set_channel()
415 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF,  in __mt7601u_phy_set_channel()
420 	mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f,  in __mt7601u_phy_set_channel()
421 		    dev->ee->chan_pwr[chan_idx] & 0x3f);  in __mt7601u_phy_set_channel()
423 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in __mt7601u_phy_set_channel()
428 	mt7601u_vco_cal(dev);  in __mt7601u_phy_set_channel()
429 	mt7601u_bbp_set_bw(dev, bw);  in __mt7601u_phy_set_channel()
430 	ret = mt7601u_set_bw_filter(dev, false);  in __mt7601u_phy_set_channel()
434 	mt7601u_apply_ch14_fixup(dev, chan->hw_value);  in __mt7601u_phy_set_channel()
435 	mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |  in __mt7601u_phy_set_channel()
440 	if (test_bit(MT7601U_STATE_SCANNING, &dev->state))  in __mt7601u_phy_set_channel()
441 		mt7601u_agc_reset(dev);  in __mt7601u_phy_set_channel()
443 	dev->chandef = *chandef;  in __mt7601u_phy_set_channel()
448 int mt7601u_phy_set_channel(struct mt7601u_dev *dev,  in mt7601u_phy_set_channel()  argument
453 	cancel_delayed_work_sync(&dev->cal_work);  in mt7601u_phy_set_channel()
454 	cancel_delayed_work_sync(&dev->freq_cal.work);  in mt7601u_phy_set_channel()
456 	mutex_lock(&dev->hw_atomic_mutex);  in mt7601u_phy_set_channel()
457 	ret = __mt7601u_phy_set_channel(dev, chandef);  in mt7601u_phy_set_channel()
458 	mutex_unlock(&dev->hw_atomic_mutex);  in mt7601u_phy_set_channel()
462 	if (test_bit(MT7601U_STATE_SCANNING, &dev->state))  in mt7601u_phy_set_channel()
465 	ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,  in mt7601u_phy_set_channel()
467 	if (dev->freq_cal.enabled)  in mt7601u_phy_set_channel()
468 		ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,  in mt7601u_phy_set_channel()
490 static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag)  in mt7601u_bbp_r47_get()  argument
493 	mt7601u_bbp_wr(dev, 47, flag);  in mt7601u_bbp_r47_get()
495 	return mt7601u_bbp_rr(dev, 49);  in mt7601u_bbp_r47_get()
498 static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev)  in mt7601u_read_bootup_temp()  argument
504 	rf_set = mt7601u_rr(dev, MT_RF_SETTING_0);  in mt7601u_read_bootup_temp()
505 	rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0);  in mt7601u_read_bootup_temp()
507 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
508 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);  in mt7601u_read_bootup_temp()
509 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);  in mt7601u_read_bootup_temp()
511 	bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10);  in mt7601u_read_bootup_temp()
513 	mt7601u_bbp_wr(dev, 22, 0x40);  in mt7601u_read_bootup_temp()
516 		bbp_val = mt7601u_bbp_rr(dev, 47);  in mt7601u_read_bootup_temp()
518 	temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP);  in mt7601u_read_bootup_temp()
520 	mt7601u_bbp_wr(dev, 22, 0);  in mt7601u_read_bootup_temp()
522 	bbp_val = mt7601u_bbp_rr(dev, 21);  in mt7601u_read_bootup_temp()
524 	mt7601u_bbp_wr(dev, 21, bbp_val);  in mt7601u_read_bootup_temp()
526 	mt7601u_bbp_wr(dev, 21, bbp_val);  in mt7601u_read_bootup_temp()
528 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
529 	mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);  in mt7601u_read_bootup_temp()
530 	mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);  in mt7601u_read_bootup_temp()
532 	trace_read_temp(dev, temp);  in mt7601u_read_bootup_temp()
536 static s8 mt7601u_read_temp(struct mt7601u_dev *dev)  in mt7601u_read_temp()  argument
542 	val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10);  in mt7601u_read_temp()
546 		val = mt7601u_bbp_rr(dev, 47);  in mt7601u_read_temp()
548 	temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP);  in mt7601u_read_temp()
550 	trace_read_temp(dev, temp);  in mt7601u_read_temp()
554 static void mt7601u_rxdc_cal(struct mt7601u_dev *dev)  in mt7601u_rxdc_cal()  argument
565 	mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);  in mt7601u_rxdc_cal()
566 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);  in mt7601u_rxdc_cal()
568 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_rxdc_cal()
571 		dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret);  in mt7601u_rxdc_cal()
576 		mt7601u_bbp_wr(dev, 158, 0x8c);  in mt7601u_rxdc_cal()
577 		if (mt7601u_bbp_rr(dev, 159) == 0x0c)  in mt7601u_rxdc_cal()
581 		dev_err(dev->dev, "%s timed out\n", __func__);  in mt7601u_rxdc_cal()
583 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_rxdc_cal()
585 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_rxdc_cal()
588 		dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret);  in mt7601u_rxdc_cal()
590 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_rxdc_cal()
593 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev)  in mt7601u_phy_recalibrate_after_assoc()  argument
595 	mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp);  in mt7601u_phy_recalibrate_after_assoc()
597 	mt7601u_rxdc_cal(dev);  in mt7601u_phy_recalibrate_after_assoc()
633 mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db)  in mt7601u_set_initial_tssi()  argument
635 	struct tssi_data *d = &dev->ee->tssi_data;  in mt7601u_set_initial_tssi()
640 	mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,  in mt7601u_set_initial_tssi()
644 static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev)  in mt7601u_tssi_dc_gain_cal()  argument
651 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);  in mt7601u_tssi_dc_gain_cal()
652 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);  in mt7601u_tssi_dc_gain_cal()
653 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_tssi_dc_gain_cal()
655 	mt7601u_bbp_wr(dev, 58, 0);  in mt7601u_tssi_dc_gain_cal()
656 	mt7601u_bbp_wr(dev, 241, 0x2);  in mt7601u_tssi_dc_gain_cal()
657 	mt7601u_bbp_wr(dev, 23, 0x8);  in mt7601u_tssi_dc_gain_cal()
658 	bbp_r47 = mt7601u_bbp_rr(dev, 47);  in mt7601u_tssi_dc_gain_cal()
661 	rf_vga = mt7601u_rf_rr(dev, 5, 3);  in mt7601u_tssi_dc_gain_cal()
662 	mt7601u_rf_wr(dev, 5, 3, 8);  in mt7601u_tssi_dc_gain_cal()
665 	rf_mixer = mt7601u_rf_rr(dev, 4, 39);  in mt7601u_tssi_dc_gain_cal()
666 	mt7601u_rf_wr(dev, 4, 39, 0);  in mt7601u_tssi_dc_gain_cal()
669 		mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0);  in mt7601u_tssi_dc_gain_cal()
671 		mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02);  in mt7601u_tssi_dc_gain_cal()
672 		mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11);  in mt7601u_tssi_dc_gain_cal()
675 		mt7601u_bbp_wr(dev, 22, 0);  in mt7601u_tssi_dc_gain_cal()
676 		mt7601u_bbp_wr(dev, 244, 0);  in mt7601u_tssi_dc_gain_cal()
678 		mt7601u_bbp_wr(dev, 21, 1);  in mt7601u_tssi_dc_gain_cal()
680 		mt7601u_bbp_wr(dev, 21, 0);  in mt7601u_tssi_dc_gain_cal()
683 		mt7601u_bbp_wr(dev, 47, 0x50);  in mt7601u_tssi_dc_gain_cal()
684 		mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40);  in mt7601u_tssi_dc_gain_cal()
687 			if (!(mt7601u_bbp_rr(dev, 47) & 0x10))  in mt7601u_tssi_dc_gain_cal()
690 			dev_err(dev->dev, "%s timed out\n", __func__);  in mt7601u_tssi_dc_gain_cal()
693 		mt7601u_bbp_wr(dev, 47, 0x40);  in mt7601u_tssi_dc_gain_cal()
694 		res[i] = mt7601u_bbp_rr(dev, 49);  in mt7601u_tssi_dc_gain_cal()
699 	dev->tssi_init = res[0];  in mt7601u_tssi_dc_gain_cal()
700 	dev->tssi_init_hvga = res[2];  in mt7601u_tssi_dc_gain_cal()
701 	dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db;  in mt7601u_tssi_dc_gain_cal()
703 	dev_dbg(dev->dev,  in mt7601u_tssi_dc_gain_cal()
705 		dev->tssi_init, tssi_init_db, dev->tssi_init_hvga,  in mt7601u_tssi_dc_gain_cal()
706 		tssi_init_hvga_db, dev->tssi_init_hvga_offset_db);  in mt7601u_tssi_dc_gain_cal()
708 	mt7601u_bbp_wr(dev, 22, 0);  in mt7601u_tssi_dc_gain_cal()
709 	mt7601u_bbp_wr(dev, 244, 0);  in mt7601u_tssi_dc_gain_cal()
711 	mt7601u_bbp_wr(dev, 21, 1);  in mt7601u_tssi_dc_gain_cal()
713 	mt7601u_bbp_wr(dev, 21, 0);  in mt7601u_tssi_dc_gain_cal()
715 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_tssi_dc_gain_cal()
716 	mt7601u_wr(dev, MT_RF_SETTING_0, 0);  in mt7601u_tssi_dc_gain_cal()
718 	mt7601u_rf_wr(dev, 5, 3, rf_vga);  in mt7601u_tssi_dc_gain_cal()
719 	mt7601u_rf_wr(dev, 4, 39, rf_mixer);  in mt7601u_tssi_dc_gain_cal()
720 	mt7601u_bbp_wr(dev, 47, bbp_r47);  in mt7601u_tssi_dc_gain_cal()
722 	mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db);  in mt7601u_tssi_dc_gain_cal()
725 static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on)  in mt7601u_temp_comp()  argument
729 	temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE;  in mt7601u_temp_comp()
730 	dev->curr_temp = temp;  in mt7601u_temp_comp()
733 	if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) {  in mt7601u_temp_comp()
734 		dev->dpd_temp = temp;  in mt7601u_temp_comp()
736 		ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);  in mt7601u_temp_comp()
740 		mt7601u_vco_cal(dev);  in mt7601u_temp_comp()
742 		dev_dbg(dev->dev, "Recalibrate DPD\n");  in mt7601u_temp_comp()
746 	if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */  in mt7601u_temp_comp()
747 		dev->pll_lock_protect =  true;  in mt7601u_temp_comp()
749 		mt7601u_rf_wr(dev, 4, 4, 6);  in mt7601u_temp_comp()
750 		mt7601u_rf_clear(dev, 4, 10, 0x30);  in mt7601u_temp_comp()
752 		dev_dbg(dev->dev, "PLL lock protect on - too cold\n");  in mt7601u_temp_comp()
753 	} else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */  in mt7601u_temp_comp()
754 		dev->pll_lock_protect = false;  in mt7601u_temp_comp()
756 		mt7601u_rf_wr(dev, 4, 4, 0);  in mt7601u_temp_comp()
757 		mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10);  in mt7601u_temp_comp()
759 		dev_dbg(dev->dev, "PLL lock protect off\n");  in mt7601u_temp_comp()
769 		return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high");  in mt7601u_temp_comp()
771 		return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal");  in mt7601u_temp_comp()
773 		return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low");  in mt7601u_temp_comp()
777 static int mt7601u_current_tx_power(struct mt7601u_dev *dev)  in mt7601u_current_tx_power()  argument
779 	return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1];  in mt7601u_current_tx_power()
782 static bool mt7601u_use_hvga(struct mt7601u_dev *dev)  in mt7601u_use_hvga()  argument
784 	return !(mt7601u_current_tx_power(dev) > 20);  in mt7601u_use_hvga()
788 mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate)  in mt7601u_phy_rf_pa_mode_val()  argument
797 		reg = dev->rf_pa_mode[0];  in mt7601u_phy_rf_pa_mode_val()
800 		reg = dev->rf_pa_mode[1];  in mt7601u_phy_rf_pa_mode_val()
808 mt7601u_tssi_params_get(struct mt7601u_dev *dev)  in mt7601u_tssi_params_get()  argument
816 	bbp_r47 = mt7601u_bbp_rr(dev, 47);  in mt7601u_tssi_params_get()
818 	p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI);  in mt7601u_tssi_params_get()
819 	dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP);  in mt7601u_tssi_params_get()
820 	pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T);  in mt7601u_tssi_params_get()
822 	p.trgt_power = mt7601u_current_tx_power(dev);  in mt7601u_tssi_params_get()
827 		rate_table = dev->ee->power_rate_table.cck;  in mt7601u_tssi_params_get()
832 		rate_table = dev->ee->power_rate_table.ofdm;  in mt7601u_tssi_params_get()
836 		tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE);  in mt7601u_tssi_params_get()
838 		rate_table = dev->ee->power_rate_table.ht;  in mt7601u_tssi_params_get()
842 	if (dev->bw == MT_BW_20)  in mt7601u_tssi_params_get()
849 	dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power);  in mt7601u_tssi_params_get()
851 	p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03,  in mt7601u_tssi_params_get()
856 		if (mt7601u_bbp_rr(dev, 4) & 0x20)  in mt7601u_tssi_params_get()
857 			p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830;  in mt7601u_tssi_params_get()
859 			p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576;  in mt7601u_tssi_params_get()
862 	p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03];  in mt7601u_tssi_params_get()
864 	p.trgt_power += dev->ee->tssi_data.tx0_delta_offset;  in mt7601u_tssi_params_get()
866 	dev_dbg(dev->dev,  in mt7601u_tssi_params_get()
868 		p.tssi0, p.trgt_power, dev->raw_temp, pkt_type);  in mt7601u_tssi_params_get()
873 static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev)  in mt7601u_tssi_read_ready()  argument
875 	return !(mt7601u_bbp_rr(dev, 47) & 0x10);  in mt7601u_tssi_read_ready()
878 static int mt7601u_tssi_cal(struct mt7601u_dev *dev)  in mt7601u_tssi_cal()  argument
888 	if (!dev->ee->tssi_enabled)  in mt7601u_tssi_cal()
891 	hvga = mt7601u_use_hvga(dev);  in mt7601u_tssi_cal()
892 	if (!dev->tssi_read_trig)  in mt7601u_tssi_cal()
893 		return mt7601u_mcu_tssi_read_kick(dev, hvga);  in mt7601u_tssi_cal()
895 	if (!mt7601u_tssi_read_ready(dev))  in mt7601u_tssi_cal()
898 	params = mt7601u_tssi_params_get(dev);  in mt7601u_tssi_cal()
900 	tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init);  in mt7601u_tssi_cal()
903 	dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n",  in mt7601u_tssi_cal()
906 	if (dev->chandef.chan->hw_value < 5)  in mt7601u_tssi_cal()
907 		tssi_offset = dev->ee->tssi_data.offset[0];  in mt7601u_tssi_cal()
908 	else if (dev->chandef.chan->hw_value < 9)  in mt7601u_tssi_cal()
909 		tssi_offset = dev->ee->tssi_data.offset[1];  in mt7601u_tssi_cal()
911 		tssi_offset = dev->ee->tssi_data.offset[2];  in mt7601u_tssi_cal()
914 		tssi_db -= dev->tssi_init_hvga_offset_db;  in mt7601u_tssi_cal()
916 	curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9);  in mt7601u_tssi_cal()
918 	dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr);  in mt7601u_tssi_cal()
921 		dev_err(dev->dev, "Error: TSSI upper saturation\n");  in mt7601u_tssi_cal()
925 		dev_err(dev->dev, "Error: TSSI lower saturation\n");  in mt7601u_tssi_cal()
929 	if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 &&  in mt7601u_tssi_cal()
930 	    (abs(diff_pwr) > abs(dev->prev_pwr_diff) ||  in mt7601u_tssi_cal()
931 	     (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff)))  in mt7601u_tssi_cal()
934 		dev->prev_pwr_diff = diff_pwr;  in mt7601u_tssi_cal()
939 	dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr);  in mt7601u_tssi_cal()
941 	val = mt7601u_rr(dev, MT_TX_ALC_CFG_1);  in mt7601u_tssi_cal()
945 	mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);  in mt7601u_tssi_cal()
947 	return mt7601u_mcu_tssi_read_kick(dev, hvga);  in mt7601u_tssi_cal()
950 static u8 mt7601u_agc_default(struct mt7601u_dev *dev)  in mt7601u_agc_default()  argument
952 	return (dev->ee->lna_gain - 8) * 2 + 0x34;  in mt7601u_agc_default()
955 static void mt7601u_agc_reset(struct mt7601u_dev *dev)  in mt7601u_agc_reset()  argument
957 	u8 agc = mt7601u_agc_default(dev);  in mt7601u_agc_reset()
959 	mt7601u_bbp_wr(dev, 66,	agc);  in mt7601u_agc_reset()
962 void mt7601u_agc_save(struct mt7601u_dev *dev)  in mt7601u_agc_save()  argument
964 	dev->agc_save = mt7601u_bbp_rr(dev, 66);  in mt7601u_agc_save()
967 void mt7601u_agc_restore(struct mt7601u_dev *dev)  in mt7601u_agc_restore()  argument
969 	mt7601u_bbp_wr(dev, 66, dev->agc_save);  in mt7601u_agc_restore()
972 static void mt7601u_agc_tune(struct mt7601u_dev *dev)  in mt7601u_agc_tune()  argument
974 	u8 val = mt7601u_agc_default(dev);  in mt7601u_agc_tune()
976 	if (test_bit(MT7601U_STATE_SCANNING, &dev->state))  in mt7601u_agc_tune()
983 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_agc_tune()
984 	if (dev->avg_rssi <= -70)  in mt7601u_agc_tune()
986 	else if (dev->avg_rssi <= -60)  in mt7601u_agc_tune()
988 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_agc_tune()
990 	if (val != mt7601u_bbp_rr(dev, 66))  in mt7601u_agc_tune()
991 		mt7601u_bbp_wr(dev, 66, val);  in mt7601u_agc_tune()
1000 	struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,  in mt7601u_phy_calibrate()  local
1003 	mt7601u_agc_tune(dev);  in mt7601u_phy_calibrate()
1004 	mt7601u_tssi_cal(dev);  in mt7601u_phy_calibrate()
1006 	if (!dev->ee->tssi_enabled)  in mt7601u_phy_calibrate()
1007 		dev->raw_temp = mt7601u_read_temp(dev);  in mt7601u_phy_calibrate()
1008 	mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */  in mt7601u_phy_calibrate()
1010 	ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,  in mt7601u_phy_calibrate()
1015 __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode)  in __mt7601u_phy_freq_cal()  argument
1019 	trace_freq_cal_offset(dev, phy_mode, last_offset);  in __mt7601u_phy_freq_cal()
1045 		dev->freq_cal.adjusting = true;  in __mt7601u_phy_freq_cal()
1047 		dev->freq_cal.adjusting = false;  in __mt7601u_phy_freq_cal()
1049 	if (!dev->freq_cal.adjusting)  in __mt7601u_phy_freq_cal()
1053 		if (dev->freq_cal.freq > 0)  in __mt7601u_phy_freq_cal()
1054 			dev->freq_cal.freq--;  in __mt7601u_phy_freq_cal()
1056 			dev->freq_cal.adjusting = false;  in __mt7601u_phy_freq_cal()
1058 		if (dev->freq_cal.freq < 0xbf)  in __mt7601u_phy_freq_cal()
1059 			dev->freq_cal.freq++;  in __mt7601u_phy_freq_cal()
1061 			dev->freq_cal.adjusting = false;  in __mt7601u_phy_freq_cal()
1064 	trace_freq_cal_adjust(dev, dev->freq_cal.freq);  in __mt7601u_phy_freq_cal()
1065 	mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq);  in __mt7601u_phy_freq_cal()
1066 	mt7601u_vco_cal(dev);  in __mt7601u_phy_freq_cal()
1068 	return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL :  in __mt7601u_phy_freq_cal()
1074 	struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,  in mt7601u_phy_freq_cal()  local
1080 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1081 	last_offset = dev->bcn_freq_off;  in mt7601u_phy_freq_cal()
1082 	phy_mode = dev->bcn_phy_mode;  in mt7601u_phy_freq_cal()
1083 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1085 	delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode);  in mt7601u_phy_freq_cal()
1086 	ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay);  in mt7601u_phy_freq_cal()
1088 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1089 	dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;  in mt7601u_phy_freq_cal()
1090 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1093 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,  in mt7601u_phy_con_cal_onoff()  argument
1097 		cancel_delayed_work_sync(&dev->freq_cal.work);  in mt7601u_phy_con_cal_onoff()
1100 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_phy_con_cal_onoff()
1101 	ether_addr_copy(dev->ap_bssid, info->bssid);  in mt7601u_phy_con_cal_onoff()
1102 	dev->avg_rssi = 0;  in mt7601u_phy_con_cal_onoff()
1103 	dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;  in mt7601u_phy_con_cal_onoff()
1104 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_phy_con_cal_onoff()
1106 	dev->freq_cal.freq = dev->ee->rf_freq_off;  in mt7601u_phy_con_cal_onoff()
1107 	dev->freq_cal.enabled = info->assoc;  in mt7601u_phy_con_cal_onoff()
1108 	dev->freq_cal.adjusting = false;  in mt7601u_phy_con_cal_onoff()
1111 		ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,  in mt7601u_phy_con_cal_onoff()
1115 static int mt7601u_init_cal(struct mt7601u_dev *dev)  in mt7601u_init_cal()  argument
1120 	dev->raw_temp = mt7601u_read_bootup_temp(dev);  in mt7601u_init_cal()
1121 	dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) *  in mt7601u_init_cal()
1123 	dev->dpd_temp = dev->curr_temp;  in mt7601u_init_cal()
1125 	mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);  in mt7601u_init_cal()
1127 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0);  in mt7601u_init_cal()
1131 	ret = mt7601u_rf_rr(dev, 0, 4);  in mt7601u_init_cal()
1135 	ret = mt7601u_rf_wr(dev, 0, 4, ret);  in mt7601u_init_cal()
1140 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0);  in mt7601u_init_cal()
1144 	mt7601u_rxdc_cal(dev);  in mt7601u_init_cal()
1146 	ret = mt7601u_set_bw_filter(dev, true);  in mt7601u_init_cal()
1149 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0);  in mt7601u_init_cal()
1152 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0);  in mt7601u_init_cal()
1155 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0);  in mt7601u_init_cal()
1158 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);  in mt7601u_init_cal()
1162 	mt7601u_rxdc_cal(dev);  in mt7601u_init_cal()
1164 	mt7601u_tssi_dc_gain_cal(dev);  in mt7601u_init_cal()
1166 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_init_cal()
1168 	mt7601u_temp_comp(dev, true);  in mt7601u_init_cal()
1173 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw)  in mt7601u_bbp_set_bw()  argument
1177 	if (bw == dev->bw) {  in mt7601u_bbp_set_bw()
1179 		mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);  in mt7601u_bbp_set_bw()
1183 	dev->bw = bw;  in mt7601u_bbp_set_bw()
1186 	old = mt7601u_rr(dev, MT_MAC_SYS_CTRL);  in mt7601u_bbp_set_bw()
1188 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);  in mt7601u_bbp_set_bw()
1189 	mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,  in mt7601u_bbp_set_bw()
1192 	mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);  in mt7601u_bbp_set_bw()
1194 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);  in mt7601u_bbp_set_bw()
1196 	return mt7601u_load_bbp_temp_table_bw(dev);  in mt7601u_bbp_set_bw()
1204 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path)  in mt7601u_set_rx_path()  argument
1206 	mt7601u_bbp_rmw(dev, 3, 0x18, path << 3);  in mt7601u_set_rx_path()
1214 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac)  in mt7601u_set_tx_dac()  argument
1216 	mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3);  in mt7601u_set_tx_dac()
1219 int mt7601u_phy_init(struct mt7601u_dev *dev)  in mt7601u_phy_init()  argument
1223 	dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0);  in mt7601u_phy_init()
1224 	dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1);  in mt7601u_phy_init()
1226 	ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off);  in mt7601u_phy_init()
1229 	ret = mt7601u_write_reg_pairs(dev, 0, rf_central,  in mt7601u_phy_init()
1233 	ret = mt7601u_write_reg_pairs(dev, 0, rf_channel,  in mt7601u_phy_init()
1237 	ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga));  in mt7601u_phy_init()
1241 	ret = mt7601u_init_cal(dev);  in mt7601u_phy_init()
1245 	dev->prev_pwr_diff = 100;  in mt7601u_phy_init()
1247 	INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate);  in mt7601u_phy_init()
1248 	INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal);  in mt7601u_phy_init()