Lines Matching refs:trans
90 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) in iwl_pcie_free_fw_monitor() argument
92 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_free_fw_monitor()
97 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, in iwl_pcie_free_fw_monitor()
106 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) in iwl_pcie_alloc_fw_monitor() argument
108 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_alloc_fw_monitor()
127 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, in iwl_pcie_alloc_fw_monitor()
144 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, in iwl_pcie_alloc_fw_monitor()
146 if (dma_mapping_error(trans->dev, phys)) { in iwl_pcie_alloc_fw_monitor()
151 IWL_INFO(trans, in iwl_pcie_alloc_fw_monitor()
161 IWL_ERR(trans, in iwl_pcie_alloc_fw_monitor()
171 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_shr() argument
173 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_read_shr()
175 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); in iwl_trans_pcie_read_shr()
178 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) in iwl_trans_pcie_write_shr() argument
180 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); in iwl_trans_pcie_write_shr()
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_write_shr()
185 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) in iwl_pcie_set_pwr() argument
187 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
190 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
191 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
195 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
203 static void iwl_pcie_apm_config(struct iwl_trans *trans) in iwl_pcie_apm_config() argument
205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apm_config()
219 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); in iwl_pcie_apm_config()
221 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); in iwl_pcie_apm_config()
222 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
225 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
226 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
228 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
236 static int iwl_pcie_apm_init(struct iwl_trans *trans) in iwl_pcie_apm_init() argument
239 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); in iwl_pcie_apm_init()
247 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
248 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
255 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
259 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); in iwl_pcie_apm_init()
265 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_init()
268 iwl_pcie_apm_config(trans); in iwl_pcie_apm_init()
271 if (trans->cfg->base_params->pll_cfg_val) in iwl_pcie_apm_init()
272 iwl_set_bit(trans, CSR_ANA_PLL_CFG, in iwl_pcie_apm_init()
273 trans->cfg->base_params->pll_cfg_val); in iwl_pcie_apm_init()
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_init()
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_init()
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); in iwl_pcie_apm_init()
294 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
309 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
310 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); in iwl_pcie_apm_init()
312 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
313 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
323 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
324 iwl_write_prph(trans, APMG_CLK_EN_REG, in iwl_pcie_apm_init()
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_init()
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, in iwl_pcie_apm_init()
337 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) in iwl_pcie_apm_lp_xtal_enable() argument
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_lp_xtal_enable()
370 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_lp_xtal_enable()
376 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
381 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); in iwl_pcie_apm_lp_xtal_enable()
383 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
392 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_lp_xtal_enable()
399 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, in iwl_pcie_apm_lp_xtal_enable()
401 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
409 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_lp_xtal_enable()
414 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); in iwl_pcie_apm_lp_xtal_enable()
415 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | in iwl_pcie_apm_lp_xtal_enable()
420 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); in iwl_pcie_apm_lp_xtal_enable()
421 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & in iwl_pcie_apm_lp_xtal_enable()
428 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_lp_xtal_enable()
435 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
439 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
443 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
448 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
453 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) in iwl_pcie_apm_stop_master() argument
458 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); in iwl_pcie_apm_stop_master()
460 ret = iwl_poll_bit(trans, CSR_RESET, in iwl_pcie_apm_stop_master()
464 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); in iwl_pcie_apm_stop_master()
466 IWL_DEBUG_INFO(trans, "stop master\n"); in iwl_pcie_apm_stop_master()
471 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) in iwl_pcie_apm_stop() argument
473 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); in iwl_pcie_apm_stop()
476 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
477 iwl_pcie_apm_init(trans); in iwl_pcie_apm_stop()
480 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
481 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_stop()
483 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { in iwl_pcie_apm_stop()
484 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
486 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_stop()
490 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
496 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
499 iwl_pcie_apm_stop_master(trans); in iwl_pcie_apm_stop()
501 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
502 iwl_pcie_apm_lp_xtal_enable(trans); in iwl_pcie_apm_stop()
507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_pcie_apm_stop()
515 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_stop()
519 static int iwl_pcie_nic_init(struct iwl_trans *trans) in iwl_pcie_nic_init() argument
521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_nic_init()
525 iwl_pcie_apm_init(trans); in iwl_pcie_nic_init()
529 iwl_pcie_set_pwr(trans, false); in iwl_pcie_nic_init()
531 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
534 iwl_pcie_rx_init(trans); in iwl_pcie_nic_init()
537 if (iwl_pcie_tx_init(trans)) in iwl_pcie_nic_init()
540 if (trans->cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
542 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); in iwl_pcie_nic_init()
543 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); in iwl_pcie_nic_init()
552 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) in iwl_pcie_set_hw_ready() argument
556 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
560 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
566 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); in iwl_pcie_set_hw_ready()
568 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); in iwl_pcie_set_hw_ready()
573 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) in iwl_pcie_prepare_card_hw() argument
579 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); in iwl_pcie_prepare_card_hw()
581 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
586 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_prepare_card_hw()
592 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_prepare_card_hw()
596 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
606 IWL_ERR(trans, "Couldn't prepare the card\n"); in iwl_pcie_prepare_card_hw()
614 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, in iwl_pcie_load_firmware_chunk() argument
617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_firmware_chunk()
622 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
626 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
630 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
634 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
639 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
645 iwl_write_direct32(trans, in iwl_pcie_load_firmware_chunk()
654 IWL_ERR(trans, "Failed to load firmware chunk!\n"); in iwl_pcie_load_firmware_chunk()
661 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, in iwl_pcie_load_section() argument
669 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", in iwl_pcie_load_section()
672 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
675 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); in iwl_pcie_load_section()
677 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
695 iwl_set_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
699 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, in iwl_pcie_load_section()
703 iwl_clear_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
707 IWL_ERR(trans, in iwl_pcie_load_section()
714 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
723 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) in iwl_pcie_rsa_race_bug_wa() argument
732 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); in iwl_pcie_rsa_race_bug_wa()
734 IWL_DEBUG_INFO(trans, in iwl_pcie_rsa_race_bug_wa()
740 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); in iwl_pcie_rsa_race_bug_wa()
741 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); in iwl_pcie_rsa_race_bug_wa()
744 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); in iwl_pcie_rsa_race_bug_wa()
745 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); in iwl_pcie_rsa_race_bug_wa()
747 iwl_write_prph(trans, RSA_ENABLE, 0); in iwl_pcie_rsa_race_bug_wa()
755 IWL_ERR(trans, "Failed to take ownership on secure machine\n"); in iwl_pcie_rsa_race_bug_wa()
759 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections_8000() argument
788 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections_8000()
794 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
799 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); in iwl_pcie_load_cpu_sections_8000()
801 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); in iwl_pcie_load_cpu_sections_8000()
808 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); in iwl_pcie_load_cpu_sections_8000()
810 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); in iwl_pcie_load_cpu_sections_8000()
815 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections() argument
844 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections()
850 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
855 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_pcie_load_cpu_sections()
856 iwl_set_bits_prph(trans, in iwl_pcie_load_cpu_sections()
868 static void iwl_pcie_apply_destination(struct iwl_trans *trans) in iwl_pcie_apply_destination() argument
870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apply_destination()
871 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; in iwl_pcie_apply_destination()
875 IWL_ERR(trans, in iwl_pcie_apply_destination()
879 IWL_INFO(trans, "Applying debug destination %s\n", in iwl_pcie_apply_destination()
883 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
885 IWL_WARN(trans, "PCI should have external buffer debug\n"); in iwl_pcie_apply_destination()
887 for (i = 0; i < trans->dbg_dest_reg_num; i++) { in iwl_pcie_apply_destination()
893 iwl_write32(trans, addr, val); in iwl_pcie_apply_destination()
896 iwl_set_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
899 iwl_clear_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
902 iwl_write_prph(trans, addr, val); in iwl_pcie_apply_destination()
905 iwl_set_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
908 iwl_clear_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
911 if (iwl_read_prph(trans, addr) & BIT(val)) { in iwl_pcie_apply_destination()
912 IWL_ERR(trans, in iwl_pcie_apply_destination()
919 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
927 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
929 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
930 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
935 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
942 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, in iwl_pcie_load_given_ucode() argument
945 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_given_ucode()
949 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode()
953 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); in iwl_pcie_load_given_ucode()
959 iwl_write_prph(trans, in iwl_pcie_load_given_ucode()
964 ret = iwl_pcie_load_cpu_sections(trans, image, 2, in iwl_pcie_load_given_ucode()
972 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { in iwl_pcie_load_given_ucode()
973 iwl_pcie_alloc_fw_monitor(trans, 0); in iwl_pcie_load_given_ucode()
976 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, in iwl_pcie_load_given_ucode()
978 iwl_write_prph(trans, MON_BUFF_END_ADDR, in iwl_pcie_load_given_ucode()
982 } else if (trans->dbg_dest_tlv) { in iwl_pcie_load_given_ucode()
983 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode()
987 iwl_write32(trans, CSR_RESET, 0); in iwl_pcie_load_given_ucode()
992 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, in iwl_pcie_load_given_ucode_8000() argument
998 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode_8000()
1001 if (trans->dbg_dest_tlv) in iwl_pcie_load_given_ucode_8000()
1002 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode_8000()
1005 ret = iwl_pcie_rsa_race_bug_wa(trans); in iwl_pcie_load_given_ucode_8000()
1011 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); in iwl_pcie_load_given_ucode_8000()
1014 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, in iwl_pcie_load_given_ucode_8000()
1020 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, in iwl_pcie_load_given_ucode_8000()
1024 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, in iwl_trans_pcie_start_fw() argument
1027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_fw()
1035 IWL_WARN(trans, in iwl_trans_pcie_start_fw()
1042 if (iwl_pcie_prepare_card_hw(trans)) { in iwl_trans_pcie_start_fw()
1043 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_start_fw()
1048 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_start_fw()
1051 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_start_fw()
1053 set_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_start_fw()
1055 clear_bit(STATUS_RFKILL, &trans->status); in iwl_trans_pcie_start_fw()
1056 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in iwl_trans_pcie_start_fw()
1062 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1064 ret = iwl_pcie_nic_init(trans); in iwl_trans_pcie_start_fw()
1066 IWL_ERR(trans, "Unable to init nic\n"); in iwl_trans_pcie_start_fw()
1071 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1072 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, in iwl_trans_pcie_start_fw()
1076 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1077 iwl_enable_interrupts(trans); in iwl_trans_pcie_start_fw()
1080 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1081 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1084 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1085 ret = iwl_pcie_load_given_ucode_8000(trans, fw); in iwl_trans_pcie_start_fw()
1087 ret = iwl_pcie_load_given_ucode(trans, fw); in iwl_trans_pcie_start_fw()
1094 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) in iwl_trans_pcie_fw_alive() argument
1096 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_fw_alive()
1097 iwl_pcie_tx_start(trans, scd_addr); in iwl_trans_pcie_fw_alive()
1100 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) in _iwl_trans_pcie_stop_device() argument
1102 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_stop_device()
1112 was_hw_rfkill = iwl_is_rfkill_set(trans); in _iwl_trans_pcie_stop_device()
1116 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1120 iwl_pcie_disable_ict(trans); in _iwl_trans_pcie_stop_device()
1129 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1130 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n"); in _iwl_trans_pcie_stop_device()
1131 iwl_pcie_tx_stop(trans); in _iwl_trans_pcie_stop_device()
1132 iwl_pcie_rx_stop(trans); in _iwl_trans_pcie_stop_device()
1135 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1136 iwl_write_prph(trans, APMG_CLK_DIS_REG, in _iwl_trans_pcie_stop_device()
1143 iwl_clear_bit(trans, CSR_GP_CNTRL, in _iwl_trans_pcie_stop_device()
1147 iwl_pcie_apm_stop(trans, false); in _iwl_trans_pcie_stop_device()
1150 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in _iwl_trans_pcie_stop_device()
1161 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1166 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1167 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1168 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1169 clear_bit(STATUS_RFKILL, &trans->status); in _iwl_trans_pcie_stop_device()
1175 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_stop_device()
1189 hw_rfkill = iwl_is_rfkill_set(trans); in _iwl_trans_pcie_stop_device()
1191 set_bit(STATUS_RFKILL, &trans->status); in _iwl_trans_pcie_stop_device()
1193 clear_bit(STATUS_RFKILL, &trans->status); in _iwl_trans_pcie_stop_device()
1195 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in _iwl_trans_pcie_stop_device()
1198 iwl_pcie_prepare_card_hw(trans); in _iwl_trans_pcie_stop_device()
1201 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) in iwl_trans_pcie_stop_device() argument
1203 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_stop_device()
1206 _iwl_trans_pcie_stop_device(trans, low_power); in iwl_trans_pcie_stop_device()
1210 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) in iwl_trans_pcie_rf_kill() argument
1213 IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rf_kill()
1217 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) in iwl_trans_pcie_rf_kill()
1218 _iwl_trans_pcie_stop_device(trans, true); in iwl_trans_pcie_rf_kill()
1221 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) in iwl_trans_pcie_d3_suspend() argument
1223 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_d3_suspend()
1225 if (trans->wowlan_d0i3) { in iwl_trans_pcie_d3_suspend()
1227 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_trans_pcie_d3_suspend()
1231 iwl_disable_interrupts(trans); in iwl_trans_pcie_d3_suspend()
1240 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_d3_suspend()
1244 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_suspend()
1246 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_suspend()
1249 if (!trans->wowlan_d0i3) { in iwl_trans_pcie_d3_suspend()
1255 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_suspend()
1258 iwl_pcie_set_pwr(trans, true); in iwl_trans_pcie_d3_suspend()
1261 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, in iwl_trans_pcie_d3_resume() argument
1269 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1279 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_d3_resume()
1281 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); in iwl_trans_pcie_d3_resume()
1282 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_trans_pcie_d3_resume()
1284 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_d3_resume()
1287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1292 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); in iwl_trans_pcie_d3_resume()
1296 iwl_pcie_set_pwr(trans, false); in iwl_trans_pcie_d3_resume()
1298 if (trans->wowlan_d0i3) { in iwl_trans_pcie_d3_resume()
1299 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1302 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_resume()
1304 ret = iwl_pcie_rx_init(trans); in iwl_trans_pcie_d3_resume()
1306 IWL_ERR(trans, in iwl_trans_pcie_d3_resume()
1312 val = iwl_read32(trans, CSR_RESET); in iwl_trans_pcie_d3_resume()
1321 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) in _iwl_trans_pcie_start_hw() argument
1323 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_start_hw()
1329 err = iwl_pcie_prepare_card_hw(trans); in _iwl_trans_pcie_start_hw()
1331 IWL_ERR(trans, "Error while preparing HW: %d\n", err); in _iwl_trans_pcie_start_hw()
1336 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in _iwl_trans_pcie_start_hw()
1340 iwl_pcie_apm_init(trans); in _iwl_trans_pcie_start_hw()
1343 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_start_hw()
1348 hw_rfkill = iwl_is_rfkill_set(trans); in _iwl_trans_pcie_start_hw()
1350 set_bit(STATUS_RFKILL, &trans->status); in _iwl_trans_pcie_start_hw()
1352 clear_bit(STATUS_RFKILL, &trans->status); in _iwl_trans_pcie_start_hw()
1354 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in _iwl_trans_pcie_start_hw()
1359 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) in iwl_trans_pcie_start_hw() argument
1361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_hw()
1365 ret = _iwl_trans_pcie_start_hw(trans, low_power); in iwl_trans_pcie_start_hw()
1371 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) in iwl_trans_pcie_op_mode_leave() argument
1373 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_op_mode_leave()
1379 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1382 iwl_pcie_apm_stop(trans, true); in iwl_trans_pcie_op_mode_leave()
1385 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1388 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_op_mode_leave()
1395 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) in iwl_trans_pcie_write8() argument
1397 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1400 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) in iwl_trans_pcie_write32() argument
1402 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1405 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) in iwl_trans_pcie_read32() argument
1407 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1410 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_prph() argument
1412 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, in iwl_trans_pcie_read_prph()
1414 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); in iwl_trans_pcie_read_prph()
1417 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_prph() argument
1420 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, in iwl_trans_pcie_write_prph()
1422 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); in iwl_trans_pcie_write_prph()
1431 static void iwl_trans_pcie_configure(struct iwl_trans *trans, in iwl_trans_pcie_configure() argument
1434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_configure()
1473 void iwl_trans_pcie_free(struct iwl_trans *trans) in iwl_trans_pcie_free() argument
1475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_free()
1479 iwl_pcie_tx_free(trans); in iwl_trans_pcie_free()
1480 iwl_pcie_rx_free(trans); in iwl_trans_pcie_free()
1482 free_irq(trans_pcie->pci_dev->irq, trans); in iwl_trans_pcie_free()
1483 iwl_pcie_free_ict(trans); in iwl_trans_pcie_free()
1493 iwl_pcie_free_fw_monitor(trans); in iwl_trans_pcie_free()
1495 iwl_trans_free(trans); in iwl_trans_pcie_free()
1498 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) in iwl_trans_pcie_set_pmi() argument
1501 set_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1503 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1506 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, in iwl_trans_pcie_grab_nic_access() argument
1510 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_grab_nic_access()
1518 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_grab_nic_access()
1520 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_grab_nic_access()
1542 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_grab_nic_access()
1547 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); in iwl_trans_pcie_grab_nic_access()
1549 u32 val = iwl_read32(trans, CSR_GP_CNTRL); in iwl_trans_pcie_grab_nic_access()
1567 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, in iwl_trans_pcie_release_nic_access() argument
1570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_release_nic_access()
1583 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
1596 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_read_mem() argument
1603 if (iwl_trans_grab_nic_access(trans, false, &flags)) { in iwl_trans_pcie_read_mem()
1604 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); in iwl_trans_pcie_read_mem()
1606 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); in iwl_trans_pcie_read_mem()
1607 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_read_mem()
1614 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_mem() argument
1621 if (iwl_trans_grab_nic_access(trans, false, &flags)) { in iwl_trans_pcie_write_mem()
1622 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); in iwl_trans_pcie_write_mem()
1624 iwl_write32(trans, HBUS_TARG_MEM_WDAT, in iwl_trans_pcie_write_mem()
1626 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_write_mem()
1633 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, in iwl_trans_pcie_freeze_txq_timer() argument
1637 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_freeze_txq_timer()
1651 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", in iwl_trans_pcie_freeze_txq_timer()
1689 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) in iwl_trans_pcie_wait_txq_empty() argument
1691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_wait_txq_empty()
1701 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { in iwl_trans_pcie_wait_txq_empty()
1711 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); in iwl_trans_pcie_wait_txq_empty()
1729 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
1734 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); in iwl_trans_pcie_wait_txq_empty()
1740 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", in iwl_trans_pcie_wait_txq_empty()
1745 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); in iwl_trans_pcie_wait_txq_empty()
1747 iwl_print_hex_error(trans, buf, sizeof(buf)); in iwl_trans_pcie_wait_txq_empty()
1750 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, in iwl_trans_pcie_wait_txq_empty()
1751 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); in iwl_trans_pcie_wait_txq_empty()
1753 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { in iwl_trans_pcie_wait_txq_empty()
1754 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); in iwl_trans_pcie_wait_txq_empty()
1758 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + in iwl_trans_pcie_wait_txq_empty()
1766 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
1769 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & in iwl_trans_pcie_wait_txq_empty()
1771 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); in iwl_trans_pcie_wait_txq_empty()
1777 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, in iwl_trans_pcie_set_bits_mask() argument
1780 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_set_bits_mask()
1784 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); in iwl_trans_pcie_set_bits_mask()
1788 void iwl_trans_pcie_ref(struct iwl_trans *trans) in iwl_trans_pcie_ref() argument
1790 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_ref()
1797 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); in iwl_trans_pcie_ref()
1802 void iwl_trans_pcie_unref(struct iwl_trans *trans) in iwl_trans_pcie_unref() argument
1804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_unref()
1811 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); in iwl_trans_pcie_unref()
1854 void iwl_pcie_dump_csr(struct iwl_trans *trans) in iwl_pcie_dump_csr() argument
1883 IWL_ERR(trans, "CSR values:\n"); in iwl_pcie_dump_csr()
1884 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " in iwl_pcie_dump_csr()
1887 IWL_ERR(trans, " %25s: 0X%08x\n", in iwl_pcie_dump_csr()
1889 iwl_read32(trans, csr_tbl[i])); in iwl_pcie_dump_csr()
1896 if (!debugfs_create_file(#name, mode, parent, trans, \
1928 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_tx_queue_read() local
1929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_tx_queue_read()
1938 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; in iwl_dbgfs_tx_queue_read()
1947 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { in iwl_dbgfs_tx_queue_read()
1967 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read() local
1968 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rx_queue_read()
1998 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read() local
1999 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_read()
2056 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write() local
2057 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_write()
2080 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write() local
2092 iwl_pcie_dump_csr(trans); in iwl_dbgfs_csr_write()
2101 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read() local
2105 ret = iwl_dump_fh(trans, &buf); in iwl_dbgfs_fh_reg_read()
2125 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, in iwl_trans_pcie_dbgfs_register() argument
2136 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); in iwl_trans_pcie_dbgfs_register()
2140 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, in iwl_trans_pcie_dbgfs_register() argument
2257 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans, in iwl_trans_pcie_dump_prph() argument
2264 if (!iwl_trans_grab_nic_access(trans, false, &flags)) in iwl_trans_pcie_dump_prph()
2286 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, in iwl_trans_pcie_dump_prph()
2291 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_dump_prph()
2296 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, in iwl_trans_pcie_dump_rbs() argument
2300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_rbs()
2315 dma_unmap_page(trans->dev, rxb->page_dma, max_len, in iwl_trans_pcie_dump_rbs()
2326 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, in iwl_trans_pcie_dump_rbs()
2339 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, in iwl_trans_pcie_dump_csr() argument
2351 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_dump_csr()
2358 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, in iwl_trans_pcie_fh_regs_dump() argument
2366 if (!iwl_trans_grab_nic_access(trans, false, &flags)) in iwl_trans_pcie_fh_regs_dump()
2374 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_fh_regs_dump()
2376 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_fh_regs_dump()
2384 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, in iwl_trans_pci_dump_marbh_monitor() argument
2393 if (!iwl_trans_grab_nic_access(trans, false, &flags)) in iwl_trans_pci_dump_marbh_monitor()
2396 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1); in iwl_trans_pci_dump_marbh_monitor()
2398 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR); in iwl_trans_pci_dump_marbh_monitor()
2399 __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0); in iwl_trans_pci_dump_marbh_monitor()
2401 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pci_dump_marbh_monitor()
2407 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, in iwl_trans_pcie_dump_monitor() argument
2411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_monitor()
2415 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || in iwl_trans_pcie_dump_monitor()
2416 trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_monitor()
2421 if (trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_monitor()
2423 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_monitor()
2424 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); in iwl_trans_pcie_dump_monitor()
2425 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); in iwl_trans_pcie_dump_monitor()
2435 cpu_to_le32(iwl_read_prph(trans, write_ptr)); in iwl_trans_pcie_dump_monitor()
2437 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); in iwl_trans_pcie_dump_monitor()
2439 cpu_to_le32(iwl_read_prph(trans, base)); in iwl_trans_pcie_dump_monitor()
2449 dma_sync_single_for_cpu(trans->dev, in iwl_trans_pcie_dump_monitor()
2458 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
2463 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_monitor()
2464 trans->dbg_dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
2465 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
2467 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
2469 iwl_trans_pci_dump_marbh_monitor(trans, in iwl_trans_pcie_dump_monitor()
2485 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, in iwl_trans_pcie_dump_data() argument
2488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_data()
2496 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status); in iwl_trans_pcie_dump_data()
2510 } else if (trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_data()
2513 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); in iwl_trans_pcie_dump_data()
2514 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); in iwl_trans_pcie_dump_data()
2516 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_data()
2517 trans->dbg_dest_tlv->base_shift; in iwl_trans_pcie_dump_data()
2518 end = iwl_read_prph(trans, end) << in iwl_trans_pcie_dump_data()
2519 trans->dbg_dest_tlv->end_shift; in iwl_trans_pcie_dump_data()
2522 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || in iwl_trans_pcie_dump_data()
2523 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_pcie_dump_data()
2524 end += (1 << trans->dbg_dest_tlv->end_shift); in iwl_trans_pcie_dump_data()
2538 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); in iwl_trans_pcie_dump_data()
2604 len += iwl_trans_pcie_dump_prph(trans, &data); in iwl_trans_pcie_dump_data()
2605 len += iwl_trans_pcie_dump_csr(trans, &data); in iwl_trans_pcie_dump_data()
2606 len += iwl_trans_pcie_fh_regs_dump(trans, &data); in iwl_trans_pcie_dump_data()
2608 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); in iwl_trans_pcie_dump_data()
2610 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); in iwl_trans_pcie_dump_data()
2664 struct iwl_trans *trans; in iwl_trans_pcie_alloc() local
2668 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), in iwl_trans_pcie_alloc()
2670 if (!trans) in iwl_trans_pcie_alloc()
2673 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS; in iwl_trans_pcie_alloc()
2675 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_alloc()
2677 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
2733 trans->dev = &pdev->dev; in iwl_trans_pcie_alloc()
2735 iwl_disable_interrupts(trans); in iwl_trans_pcie_alloc()
2748 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
2755 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { in iwl_trans_pcie_alloc()
2758 trans->hw_rev = (trans->hw_rev & 0xfff0) | in iwl_trans_pcie_alloc()
2759 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); in iwl_trans_pcie_alloc()
2761 ret = iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_alloc()
2763 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_alloc()
2771 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_alloc()
2775 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_alloc()
2780 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); in iwl_trans_pcie_alloc()
2784 if (iwl_trans_grab_nic_access(trans, false, &flags)) { in iwl_trans_pcie_alloc()
2787 hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG); in iwl_trans_pcie_alloc()
2789 __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step); in iwl_trans_pcie_alloc()
2790 hw_step = __iwl_read_prph(trans, AUX_MISC_REG); in iwl_trans_pcie_alloc()
2793 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | in iwl_trans_pcie_alloc()
2795 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_alloc()
2799 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
2800 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
2806 ret = iwl_pcie_alloc_ict(trans); in iwl_trans_pcie_alloc()
2812 IRQF_SHARED, DRV_NAME, trans); in iwl_trans_pcie_alloc()
2814 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
2819 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND; in iwl_trans_pcie_alloc()
2821 return trans; in iwl_trans_pcie_alloc()
2824 iwl_pcie_free_ict(trans); in iwl_trans_pcie_alloc()
2832 iwl_trans_free(trans); in iwl_trans_pcie_alloc()