Lines Matching refs:dbg_dest_tlv
871 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; in iwl_pcie_apply_destination()
982 } else if (trans->dbg_dest_tlv) { in iwl_pcie_load_given_ucode()
1001 if (trans->dbg_dest_tlv) in iwl_pcie_load_given_ucode_8000()
2416 trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_monitor()
2421 if (trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_monitor()
2423 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_monitor()
2424 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); in iwl_trans_pcie_dump_monitor()
2425 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); in iwl_trans_pcie_dump_monitor()
2458 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
2464 trans->dbg_dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
2467 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
2510 } else if (trans->dbg_dest_tlv) { in iwl_trans_pcie_dump_data()
2513 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); in iwl_trans_pcie_dump_data()
2514 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); in iwl_trans_pcie_dump_data()
2517 trans->dbg_dest_tlv->base_shift; in iwl_trans_pcie_dump_data()
2519 trans->dbg_dest_tlv->end_shift; in iwl_trans_pcie_dump_data()
2523 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_pcie_dump_data()
2524 end += (1 << trans->dbg_dest_tlv->end_shift); in iwl_trans_pcie_dump_data()