Lines Matching refs:CSR_BASE
85 #define CSR_BASE (0x000) macro
87 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
88 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
89 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
90 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
91 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
92 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
93 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
94 #define CSR_GP_CNTRL (CSR_BASE+0x024)
97 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
107 #define CSR_HW_REV (CSR_BASE+0x028)
115 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
116 #define CSR_EEPROM_GP (CSR_BASE+0x030)
117 #define CSR_OTP_GP_REG (CSR_BASE+0x034)
119 #define CSR_GIO_REG (CSR_BASE+0x03C)
120 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
121 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
127 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
128 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
129 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
130 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
132 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
134 #define CSR_LED_REG (CSR_BASE+0x094)
135 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
136 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
140 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
143 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
148 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
149 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
160 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
162 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
163 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
455 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
456 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)