Lines Matching refs:cpu_to_le16
519 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
521 #define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
523 #define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
525 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
527 #define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
529 #define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
531 #define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
814 #define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
815 #define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
816 #define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
817 #define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
818 #define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
821 #define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
823 #define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
826 #define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
827 #define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
1054 #define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1055 #define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1056 #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1057 #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1060 #define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1924 #define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1925 #define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1926 #define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1927 #define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1928 #define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1929 #define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1930 #define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1931 #define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
2158 #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2159 #define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2160 #define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2161 #define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2162 #define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2163 #define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2164 #define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2165 #define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2166 #define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2167 #define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2168 #define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2308 #define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2309 #define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
3037 #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3038 #define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3039 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3040 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3041 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3042 #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3043 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3044 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3045 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3046 #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3047 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3049 #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3050 #define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3051 #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3052 #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3053 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3054 #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3055 #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3056 #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3057 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3058 #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3059 #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3063 #define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3064 #define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3228 #define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)