Lines Matching refs:ipw_write32
375 #define ipw_write32(ipw, ofs, val) do { \ macro
575 ipw_write32(priv, reg, ipw_read32(priv, reg) | mask); in ipw_set_bit()
581 ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask); in ipw_clear_bit()
589 ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL); in __ipw_enable_interrupts()
597 ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL); in __ipw_disable_interrupts()
2745 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0); in ipw_eeprom_init_sram()
2750 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1); in ipw_eeprom_init_sram()
3113 ipw_write32(priv, addr, 0); in ipw_load_ucode()
3317 ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER); in ipw_stop_nic()
3359 ipw_write32(priv, IPW_READ_INT_REGISTER, in ipw_init_nic()
3557 ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL); in ipw_load()
3561 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL); in ipw_load()
3594 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_BIT_FW_INITIALIZATION_DONE); in ipw_load()
3616 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0); in ipw_load()
3625 ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL); in ipw_load()
3627 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL); in ipw_load()
3654 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_BIT_FW_INITIALIZATION_DONE); in ipw_load()
3668 ipw_write32(priv, IPW_RX_READ_INDEX, priv->rxq->read); in ipw_load()
3671 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL); in ipw_load()
3782 ipw_write32(priv, base, q->dma_addr); in ipw_queue_init()
3783 ipw_write32(priv, size, count); in ipw_queue_init()
3784 ipw_write32(priv, read, 0); in ipw_queue_init()
3785 ipw_write32(priv, write, 0); in ipw_queue_init()
5083 ipw_write32(priv, q->reg_w, q->first_empty); in ipw_queue_tx_hcmd()
5177 ipw_write32(priv, IPW_RFDS_TABLE_LOWER + rxq->write * RFD_SIZE, in ipw_rx_queue_restock()
5192 ipw_write32(priv, IPW_RX_WRITE_INDEX, rxq->write); in ipw_rx_queue_restock()
10297 ipw_write32(priv, q->reg_w, q->first_empty); in ipw_tx_skb()
10557 ipw_write32(priv, IPW_INTA_RW, inta); in ipw_isr()