414 #define ipw_read32(ipw, ofs) ({ \  macro
575 	ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);  in ipw_set_bit()
581 	ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);  in ipw_clear_bit()
738 		*((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);  in ipw_get_ordinal()
835 	priv->table0_len = ipw_read32(priv, priv->table0_addr);  in ipw_init_ordinals()
840 	priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);  in ipw_init_ordinals()
846 	priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);  in ipw_init_ordinals()
1231 	return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));  in ipw_get_event_log_len()
1240 		base = ipw_read32(priv, IPW_EVENT_LOG);  in ipw_capture_event_log()
1250 	u32 base = ipw_read32(priv, IPW_ERROR_LOG);  in ipw_alloc_error_log()
1747 		reg = ipw_read32(priv, priv->direct_dword);  in show_direct_dword()
1769 	if (0 == (ipw_read32(priv, 0x30) & 0x10000)) {  in rf_kill_active()
1979 	inta = ipw_read32(priv, IPW_INTA_RW);  in ipw_irq_tasklet()
1980 	inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);  in ipw_irq_tasklet()
3035 	return ipw_read32(priv, 0x90) == 0xd55555d5;  in ipw_alive()
3045 		if ((ipw_read32(priv, addr) & mask) == mask)  in ipw_poll_bit()
3632 	if (ipw_read32(priv, IPW_INTA_RW) & IPW_INTA_BIT_PARITY_ERROR) {  in ipw_load()
5037 	hw_tail = ipw_read32(priv, q->reg_r);  in ipw_queue_tx_reclaim()
6159 	reg = ipw_read32(priv, IPW_MEM_FIXED_OVERRIDE);  in ipw_set_fixed_rate()
8284 	r = ipw_read32(priv, IPW_RX_READ_INDEX);  in ipw_rx()
8285 	w = ipw_read32(priv, IPW_RX_WRITE_INDEX);  in ipw_rx()
10538 	inta = ipw_read32(priv, IPW_INTA_RW);  in ipw_isr()
10539 	inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);  in ipw_isr()