Lines Matching refs:ops
235 const struct brcmf_buscore_ops *ops; member
253 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); in brcmf_chip_sb_corerev()
265 regdata = ci->ops->read32(ci->ctx, address); in brcmf_chip_sb_iscoreup()
278 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_iscoreup()
281 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); in brcmf_chip_ai_iscoreup()
295 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
299 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
305 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
306 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_coredisable()
309 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
311 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)) in brcmf_chip_sb_coredisable()
314 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); in brcmf_chip_sb_coredisable()
318 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); in brcmf_chip_sb_coredisable()
320 val = ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
323 ci->ops->write32(ci->ctx, in brcmf_chip_sb_coredisable()
325 val = ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
328 SPINWAIT((ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
336 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val); in brcmf_chip_sb_coredisable()
337 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_coredisable()
341 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); in brcmf_chip_sb_coredisable()
343 val = ci->ops->read32(ci->ctx, in brcmf_chip_sb_coredisable()
346 ci->ops->write32(ci->ctx, in brcmf_chip_sb_coredisable()
352 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_coredisable()
366 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); in brcmf_chip_ai_coredisable()
371 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_coredisable()
373 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_coredisable()
376 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, in brcmf_chip_ai_coredisable()
381 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) != in brcmf_chip_ai_coredisable()
386 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_coredisable()
388 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_coredisable()
411 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_resetcore()
414 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_resetcore()
418 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); in brcmf_chip_sb_resetcore()
420 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0); in brcmf_chip_sb_resetcore()
422 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate)); in brcmf_chip_sb_resetcore()
425 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata); in brcmf_chip_sb_resetcore()
429 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_resetcore()
431 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_resetcore()
435 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), in brcmf_chip_sb_resetcore()
437 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); in brcmf_chip_sb_resetcore()
453 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) & in brcmf_chip_ai_resetcore()
455 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0); in brcmf_chip_ai_resetcore()
462 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, in brcmf_chip_ai_resetcore()
464 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_resetcore()
542 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); in brcmf_chip_core_read32()
548 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); in brcmf_chip_core_write32()
758 val = ci->ops->read32(ci->ctx, *eromaddr); in brcmf_chip_dmp_get_desc()
849 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr)); in brcmf_chip_dmp_erom_scan()
909 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid)); in brcmf_chip_recognition()
965 if (ci->ops->reset) { in brcmf_chip_recognition()
966 ci->ops->reset(ci->ctx, &ci->pub); in brcmf_chip_recognition()
993 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL); in brcmf_chip_disable_arm()
1017 pub->cc_caps = chip->ops->read32(chip->ctx, in brcmf_chip_setup()
1022 val = chip->ops->read32(chip->ctx, in brcmf_chip_setup()
1032 if (chip->ops->setup) in brcmf_chip_setup()
1033 ret = chip->ops->setup(chip->ctx, pub); in brcmf_chip_setup()
1039 const struct brcmf_buscore_ops *ops) in brcmf_chip_attach() argument
1044 if (WARN_ON(!ops->read32)) in brcmf_chip_attach()
1046 if (WARN_ON(!ops->write32)) in brcmf_chip_attach()
1048 if (WARN_ON(!ops->prepare)) in brcmf_chip_attach()
1050 if (WARN_ON(!ops->activate)) in brcmf_chip_attach()
1061 chip->ops = ops; in brcmf_chip_attach()
1064 err = ops->prepare(ctx); in brcmf_chip_attach()
1180 chip->ops->activate(chip->ctx, &chip->pub, 0); in brcmf_chip_cm3_set_active()
1206 chip->ops->activate(chip->ctx, &chip->pub, rstvec); in brcmf_chip_cr4_set_active()
1233 chip->ops->activate(chip->ctx, &chip->pub, rstvec); in brcmf_chip_ca7_set_active()
1312 chip->ops->write32(chip->ctx, addr, 3); in brcmf_chip_sr_capable()
1314 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1318 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1322 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()
1327 reg = chip->ops->read32(chip->ctx, addr); in brcmf_chip_sr_capable()