Lines Matching refs:dev
106 static inline bool b43_nphy_ipa(struct b43_wldev *dev) in b43_nphy_ipa() argument
108 enum ieee80211_band band = b43_current_band(dev->wl); in b43_nphy_ipa()
109 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) || in b43_nphy_ipa()
110 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)); in b43_nphy_ipa()
114 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) in b43_nphy_get_rx_core_state() argument
116 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >> in b43_nphy_get_rx_core_state()
125 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, in b43_nphy_force_rf_sequence() argument
137 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); in b43_nphy_force_rf_sequence()
141 b43_phy_set(dev, B43_NPHY_RFSEQMODE, in b43_nphy_force_rf_sequence()
143 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); in b43_nphy_force_rf_sequence()
145 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) in b43_nphy_force_rf_sequence()
149 b43err(dev->wl, "RF sequence status timeout\n"); in b43_nphy_force_rf_sequence()
151 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); in b43_nphy_force_rf_sequence()
154 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override_rev19() argument
162 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override_rev7() argument
166 struct b43_phy *phy = &dev->phy; in b43_nphy_rf_ctl_override_rev7()
182 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override); in b43_nphy_rf_ctl_override_rev7()
186 b43err(dev->wl, "Invalid override value %d\n", override); in b43_nphy_rf_ctl_override_rev7()
195 b43_phy_mask(dev, en_addr, ~en_mask); in b43_nphy_rf_ctl_override_rev7()
197 b43_phy_mask(dev, val_addr, ~e->val_mask); in b43_nphy_rf_ctl_override_rev7()
200 b43_phy_set(dev, en_addr, en_mask); in b43_nphy_rf_ctl_override_rev7()
202 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); in b43_nphy_rf_ctl_override_rev7()
209 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, in b43_nphy_rf_ctl_override_one_to_many() argument
213 struct b43_phy *phy = &dev->phy; in b43_nphy_rf_ctl_override_one_to_many()
220 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
221 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
222 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
225 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
226 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
227 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
228 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
229 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
232 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
233 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
234 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
235 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
239 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
241 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
245 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
247 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
253 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override() argument
262 if (dev->phy.rev >= 3) { in b43_nphy_rf_ctl_override()
266 b43err(dev->wl, in b43_nphy_rf_ctl_override()
278 b43_phy_mask(dev, en_addr, ~(field)); in b43_nphy_rf_ctl_override()
279 b43_phy_mask(dev, val_addr, in b43_nphy_rf_ctl_override()
283 b43_phy_set(dev, en_addr, field); in b43_nphy_rf_ctl_override()
284 b43_phy_maskset(dev, val_addr, in b43_nphy_rf_ctl_override()
293 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); in b43_nphy_rf_ctl_override()
296 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); in b43_nphy_rf_ctl_override()
301 b43err(dev->wl, in b43_nphy_rf_ctl_override()
316 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), in b43_nphy_rf_ctl_override()
319 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rf_ctl_override()
320 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_override()
323 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); in b43_nphy_rf_ctl_override()
328 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev, in b43_nphy_rf_ctl_intc_override_rev7() argument
346 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override_rev7()
347 b43_phy_mask(dev, 0x2ff, ~0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
348 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rf_ctl_intc_override_rev7()
351 b43_phy_maskset(dev, reg, ~0xC0, value << 6); in b43_nphy_rf_ctl_intc_override_rev7()
352 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override_rev7()
354 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); in b43_nphy_rf_ctl_intc_override_rev7()
355 b43_phy_set(dev, 0x2ff, 0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
356 b43_phy_set(dev, 0x2ff, 0x0001); in b43_nphy_rf_ctl_intc_override_rev7()
360 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) in b43_nphy_rf_ctl_intc_override_rev7()
364 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
365 b43_phy_set(dev, reg, 0x1000); in b43_nphy_rf_ctl_intc_override_rev7()
368 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override_rev7()
377 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
378 b43_phy_mask(dev, reg, ~tmp2); in b43_nphy_rf_ctl_intc_override_rev7()
381 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override_rev7()
390 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
391 b43_phy_mask(dev, reg, ~tmp2); in b43_nphy_rf_ctl_intc_override_rev7()
398 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev, in b43_nphy_rf_ctl_intc_override() argument
405 if (dev->phy.rev >= 7) { in b43_nphy_rf_ctl_intc_override()
406 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value, in b43_nphy_rf_ctl_intc_override()
411 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_rf_ctl_intc_override()
419 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override()
423 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override()
424 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rf_ctl_intc_override()
428 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, in b43_nphy_rf_ctl_intc_override()
430 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, in b43_nphy_rf_ctl_intc_override()
432 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_intc_override()
435 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) { in b43_nphy_rf_ctl_intc_override()
442 b43err(dev->wl, in b43_nphy_rf_ctl_intc_override()
444 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, in b43_nphy_rf_ctl_intc_override()
447 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, in b43_nphy_rf_ctl_intc_override()
449 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rf_ctl_intc_override()
451 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_intc_override()
454 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) { in b43_nphy_rf_ctl_intc_override()
461 b43err(dev->wl, in b43_nphy_rf_ctl_intc_override()
463 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rf_ctl_intc_override()
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
475 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
478 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
485 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
488 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
495 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
506 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, in b43_nphy_write_clip_detection() argument
509 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); in b43_nphy_write_clip_detection()
510 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); in b43_nphy_write_clip_detection()
514 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) in b43_nphy_read_clip_detection() argument
516 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); in b43_nphy_read_clip_detection()
517 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); in b43_nphy_read_clip_detection()
521 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) in b43_nphy_classifier() argument
525 if (dev->dev->core_rev == 16) in b43_nphy_classifier()
526 b43_mac_suspend(dev); in b43_nphy_classifier()
528 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); in b43_nphy_classifier()
533 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); in b43_nphy_classifier()
535 if (dev->dev->core_rev == 16) in b43_nphy_classifier()
536 b43_mac_enable(dev); in b43_nphy_classifier()
542 static void b43_nphy_reset_cca(struct b43_wldev *dev) in b43_nphy_reset_cca() argument
546 b43_phy_force_clock(dev, 1); in b43_nphy_reset_cca()
547 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_nphy_reset_cca()
548 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); in b43_nphy_reset_cca()
550 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); in b43_nphy_reset_cca()
551 b43_phy_force_clock(dev, 0); in b43_nphy_reset_cca()
552 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_reset_cca()
556 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) in b43_nphy_stay_in_carrier_search() argument
558 struct b43_phy *phy = &dev->phy; in b43_nphy_stay_in_carrier_search()
564 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); in b43_nphy_stay_in_carrier_search()
565 b43_nphy_classifier(dev, 0x7, in b43_nphy_stay_in_carrier_search()
567 b43_nphy_read_clip_detection(dev, nphy->clip_state); in b43_nphy_stay_in_carrier_search()
568 b43_nphy_write_clip_detection(dev, clip); in b43_nphy_stay_in_carrier_search()
570 b43_nphy_reset_cca(dev); in b43_nphy_stay_in_carrier_search()
573 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); in b43_nphy_stay_in_carrier_search()
574 b43_nphy_write_clip_detection(dev, nphy->clip_state); in b43_nphy_stay_in_carrier_search()
580 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) in b43_nphy_read_lpf_ctl() argument
583 offset = b43_is_40mhz(dev) ? 0x159 : 0x154; in b43_nphy_read_lpf_ctl()
584 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; in b43_nphy_read_lpf_ctl()
588 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) in b43_nphy_adjust_lna_gain_table() argument
590 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_adjust_lna_gain_table()
600 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_adjust_lna_gain_table()
603 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_adjust_lna_gain_table()
607 tmp = 40370 - 315 * dev->phy.channel; in b43_nphy_adjust_lna_gain_table()
609 tmp = 23242 - 224 * dev->phy.channel; in b43_nphy_adjust_lna_gain_table()
629 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); in b43_nphy_adjust_lna_gain_table()
634 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, in b43_nphy_adjust_lna_gain_table()
636 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, in b43_nphy_adjust_lna_gain_table()
640 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_adjust_lna_gain_table()
644 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, in b43_nphy_set_rf_sequence() argument
647 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_set_rf_sequence()
649 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; in b43_nphy_set_rf_sequence()
654 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_set_rf_sequence()
656 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); in b43_nphy_set_rf_sequence()
657 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); in b43_nphy_set_rf_sequence()
660 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); in b43_nphy_set_rf_sequence()
661 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); in b43_nphy_set_rf_sequence()
665 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_set_rf_sequence()
672 static void b43_radio_2057_chantab_upload(struct b43_wldev *dev, in b43_radio_2057_chantab_upload() argument
677 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); in b43_radio_2057_chantab_upload()
678 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); in b43_radio_2057_chantab_upload()
679 …b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextal… in b43_radio_2057_chantab_upload()
680 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); in b43_radio_2057_chantab_upload()
681 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); in b43_radio_2057_chantab_upload()
682 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); in b43_radio_2057_chantab_upload()
683 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); in b43_radio_2057_chantab_upload()
684 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); in b43_radio_2057_chantab_upload()
685 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); in b43_radio_2057_chantab_upload()
686 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); in b43_radio_2057_chantab_upload()
687 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); in b43_radio_2057_chantab_upload()
688 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); in b43_radio_2057_chantab_upload()
689 …b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0… in b43_radio_2057_chantab_upload()
690 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); in b43_radio_2057_chantab_upload()
691 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); in b43_radio_2057_chantab_upload()
692 …b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1… in b43_radio_2057_chantab_upload()
693 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); in b43_radio_2057_chantab_upload()
694 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); in b43_radio_2057_chantab_upload()
697 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); in b43_radio_2057_chantab_upload()
698 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); in b43_radio_2057_chantab_upload()
699 …b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsiz… in b43_radio_2057_chantab_upload()
700 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); in b43_radio_2057_chantab_upload()
701 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); in b43_radio_2057_chantab_upload()
702 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); in b43_radio_2057_chantab_upload()
703 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); in b43_radio_2057_chantab_upload()
704 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); in b43_radio_2057_chantab_upload()
705 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); in b43_radio_2057_chantab_upload()
706 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); in b43_radio_2057_chantab_upload()
707 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); in b43_radio_2057_chantab_upload()
708 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); in b43_radio_2057_chantab_upload()
709 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); in b43_radio_2057_chantab_upload()
710 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); in b43_radio_2057_chantab_upload()
711 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); in b43_radio_2057_chantab_upload()
712 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); in b43_radio_2057_chantab_upload()
713 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); in b43_radio_2057_chantab_upload()
714 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); in b43_radio_2057_chantab_upload()
715 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); in b43_radio_2057_chantab_upload()
716 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); in b43_radio_2057_chantab_upload()
717 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); in b43_radio_2057_chantab_upload()
718 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); in b43_radio_2057_chantab_upload()
719 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); in b43_radio_2057_chantab_upload()
720 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); in b43_radio_2057_chantab_upload()
721 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); in b43_radio_2057_chantab_upload()
722 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); in b43_radio_2057_chantab_upload()
723 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); in b43_radio_2057_chantab_upload()
724 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); in b43_radio_2057_chantab_upload()
728 static void b43_radio_2057_setup(struct b43_wldev *dev, in b43_radio_2057_setup() argument
732 struct b43_phy *phy = &dev->phy; in b43_radio_2057_setup()
734 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g); in b43_radio_2057_setup()
739 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_radio_2057_setup()
740 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); in b43_radio_2057_setup()
741 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
742 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
743 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
745 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); in b43_radio_2057_setup()
746 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
747 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
748 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
752 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); in b43_radio_2057_setup()
753 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); in b43_radio_2057_setup()
754 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_radio_2057_setup()
755 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); in b43_radio_2057_setup()
756 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); in b43_radio_2057_setup()
758 if (b43_is_40mhz(dev)) { in b43_radio_2057_setup()
761 b43_radio_write(dev, in b43_radio_2057_setup()
764 b43_radio_write(dev, in b43_radio_2057_setup()
771 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); in b43_radio_2057_setup()
772 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
773 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); in b43_radio_2057_setup()
774 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); in b43_radio_2057_setup()
778 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_radio_2057_setup()
782 if (b43_nphy_ipa(dev)) { in b43_radio_2057_setup()
796 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, in b43_radio_2057_setup()
799 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, in b43_radio_2057_setup()
802 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, in b43_radio_2057_setup()
805 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, in b43_radio_2057_setup()
812 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); in b43_radio_2057_setup()
813 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); in b43_radio_2057_setup()
814 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); in b43_radio_2057_setup()
815 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); in b43_radio_2057_setup()
822 static u8 b43_radio_2057_rcal(struct b43_wldev *dev) in b43_radio_2057_rcal() argument
824 struct b43_phy *phy = &dev->phy; in b43_radio_2057_rcal()
846 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]); in b43_radio_2057_rcal()
848 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]); in b43_radio_2057_rcal()
852 b43_phy_write(dev, phy_to_store[i], 0); in b43_radio_2057_rcal()
853 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); in b43_radio_2057_rcal()
854 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); in b43_radio_2057_rcal()
855 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); in b43_radio_2057_rcal()
856 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); in b43_radio_2057_rcal()
857 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); in b43_radio_2057_rcal()
858 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); in b43_radio_2057_rcal()
862 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); in b43_radio_2057_rcal()
864 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
865 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); in b43_radio_2057_rcal()
868 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
869 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
870 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
871 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); in b43_radio_2057_rcal()
874 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
875 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2); in b43_radio_2057_rcal()
876 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
877 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
878 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); in b43_radio_2057_rcal()
879 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
884 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); in b43_radio_2057_rcal()
888 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); in b43_radio_2057_rcal()
892 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); in b43_radio_2057_rcal()
895 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { in b43_radio_2057_rcal()
896 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rcal()
899 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; in b43_radio_2057_rcal()
902 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); in b43_radio_2057_rcal()
906 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]); in b43_radio_2057_rcal()
908 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]); in b43_radio_2057_rcal()
913 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); in b43_radio_2057_rcal()
914 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, in b43_radio_2057_rcal()
918 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); in b43_radio_2057_rcal()
919 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); in b43_radio_2057_rcal()
922 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
925 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
926 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); in b43_radio_2057_rcal()
936 static u16 b43_radio_2057_rccal(struct b43_wldev *dev) in b43_radio_2057_rccal() argument
938 struct b43_phy *phy = &dev->phy; in b43_radio_2057_rccal()
945 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
946 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); in b43_radio_2057_rccal()
948 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
949 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); in b43_radio_2057_rccal()
951 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
954 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
955 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
957 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
959 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
964 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
965 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
967 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
968 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); in b43_radio_2057_rccal()
970 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
974 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
976 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
978 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
980 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
985 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
986 b43_radio_write(dev, R2057_RCCAL_X1, 0x28); in b43_radio_2057_rccal()
987 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
989 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
990 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
991 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); in b43_radio_2057_rccal()
996 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
998 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
1000 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rccal()
1003 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP); in b43_radio_2057_rccal()
1005 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
1009 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
1011 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
1016 static void b43_radio_2057_init_pre(struct b43_wldev *dev) in b43_radio_2057_init_pre() argument
1018 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU); in b43_radio_2057_init_pre()
1020 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE); in b43_radio_2057_init_pre()
1021 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE); in b43_radio_2057_init_pre()
1022 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU); in b43_radio_2057_init_pre()
1025 static void b43_radio_2057_init_post(struct b43_wldev *dev) in b43_radio_2057_init_post() argument
1027 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); in b43_radio_2057_init_post()
1030 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); in b43_radio_2057_init_post()
1032 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); in b43_radio_2057_init_post()
1033 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); in b43_radio_2057_init_post()
1035 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); in b43_radio_2057_init_post()
1036 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); in b43_radio_2057_init_post()
1038 if (dev->phy.do_full_init) { in b43_radio_2057_init_post()
1039 b43_radio_2057_rcal(dev); in b43_radio_2057_init_post()
1040 b43_radio_2057_rccal(dev); in b43_radio_2057_init_post()
1042 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); in b43_radio_2057_init_post()
1046 static void b43_radio_2057_init(struct b43_wldev *dev) in b43_radio_2057_init() argument
1048 b43_radio_2057_init_pre(dev); in b43_radio_2057_init()
1049 r2057_upload_inittabs(dev); in b43_radio_2057_init()
1050 b43_radio_2057_init_post(dev); in b43_radio_2057_init()
1057 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev, in b43_chantab_radio_2056_upload() argument
1060 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); in b43_chantab_radio_2056_upload()
1061 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); in b43_chantab_radio_2056_upload()
1062 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); in b43_chantab_radio_2056_upload()
1063 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); in b43_chantab_radio_2056_upload()
1064 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); in b43_chantab_radio_2056_upload()
1065 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, in b43_chantab_radio_2056_upload()
1067 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, in b43_chantab_radio_2056_upload()
1069 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3, in b43_chantab_radio_2056_upload()
1071 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, in b43_chantab_radio_2056_upload()
1073 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5, in b43_chantab_radio_2056_upload()
1075 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27, in b43_chantab_radio_2056_upload()
1077 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28, in b43_chantab_radio_2056_upload()
1079 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29, in b43_chantab_radio_2056_upload()
1081 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1, in b43_chantab_radio_2056_upload()
1083 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); in b43_chantab_radio_2056_upload()
1084 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); in b43_chantab_radio_2056_upload()
1085 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); in b43_chantab_radio_2056_upload()
1087 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE, in b43_chantab_radio_2056_upload()
1089 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE, in b43_chantab_radio_2056_upload()
1092 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1094 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1096 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1098 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1100 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1102 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1104 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1106 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1109 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE, in b43_chantab_radio_2056_upload()
1111 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE, in b43_chantab_radio_2056_upload()
1114 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1116 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1118 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1120 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1122 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1124 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1126 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1128 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1133 static void b43_radio_2056_setup(struct b43_wldev *dev, in b43_radio_2056_setup() argument
1136 struct b43_phy *phy = &dev->phy; in b43_radio_2056_setup()
1137 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_radio_2056_setup()
1138 enum ieee80211_band band = b43_current_band(dev->wl); in b43_radio_2056_setup()
1146 B43_WARN_ON(dev->phy.rev < 3); in b43_radio_2056_setup()
1149 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 || in b43_radio_2056_setup()
1150 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 || in b43_radio_2056_setup()
1151 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) && in b43_radio_2056_setup()
1152 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC); in b43_radio_2056_setup()
1154 b43_chantab_radio_2056_upload(dev, e); in b43_radio_2056_setup()
1155 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ); in b43_radio_2056_setup()
1158 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_radio_2056_setup()
1159 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1161 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || in b43_radio_2056_setup()
1162 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { in b43_radio_2056_setup()
1163 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); in b43_radio_2056_setup()
1164 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); in b43_radio_2056_setup()
1166 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); in b43_radio_2056_setup()
1167 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); in b43_radio_2056_setup()
1171 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_radio_2056_setup()
1172 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); in b43_radio_2056_setup()
1173 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); in b43_radio_2056_setup()
1174 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); in b43_radio_2056_setup()
1175 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); in b43_radio_2056_setup()
1178 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_radio_2056_setup()
1179 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1180 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1181 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); in b43_radio_2056_setup()
1182 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); in b43_radio_2056_setup()
1185 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) { in b43_radio_2056_setup()
1188 if (dev->phy.rev >= 5) { in b43_radio_2056_setup()
1189 b43_radio_write(dev, in b43_radio_2056_setup()
1192 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || in b43_radio_2056_setup()
1193 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { in b43_radio_2056_setup()
1212 b43_radio_write(dev, in b43_radio_2056_setup()
1215 b43_radio_write(dev, in b43_radio_2056_setup()
1218 b43_radio_write(dev, in b43_radio_2056_setup()
1221 b43_radio_write(dev, in b43_radio_2056_setup()
1224 b43_radio_write(dev, in b43_radio_2056_setup()
1227 b43_radio_write(dev, in b43_radio_2056_setup()
1230 b43_radio_write(dev, in b43_radio_2056_setup()
1234 bias = b43_is_40mhz(dev) ? 0x40 : 0x20; in b43_radio_2056_setup()
1235 b43_radio_write(dev, in b43_radio_2056_setup()
1238 b43_radio_write(dev, in b43_radio_2056_setup()
1241 b43_radio_write(dev, in b43_radio_2056_setup()
1245 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); in b43_radio_2056_setup()
1247 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) { in b43_radio_2056_setup()
1279 b43_radio_write(dev, in b43_radio_2056_setup()
1281 b43_radio_write(dev, in b43_radio_2056_setup()
1283 b43_radio_write(dev, in b43_radio_2056_setup()
1285 b43_radio_write(dev, in b43_radio_2056_setup()
1287 b43_radio_write(dev, in b43_radio_2056_setup()
1289 b43_radio_write(dev, in b43_radio_2056_setup()
1291 b43_radio_write(dev, in b43_radio_2056_setup()
1293 b43_radio_write(dev, in b43_radio_2056_setup()
1295 b43_radio_write(dev, in b43_radio_2056_setup()
1297 b43_radio_write(dev, in b43_radio_2056_setup()
1304 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); in b43_radio_2056_setup()
1305 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1306 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); in b43_radio_2056_setup()
1307 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1308 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); in b43_radio_2056_setup()
1312 static u8 b43_radio_2056_rcal(struct b43_wldev *dev) in b43_radio_2056_rcal() argument
1314 struct b43_phy *phy = &dev->phy; in b43_radio_2056_rcal()
1320 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2); in b43_radio_2056_rcal()
1321 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); in b43_radio_2056_rcal()
1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1326 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); in b43_radio_2056_rcal()
1328 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, in b43_radio_2056_rcal()
1330 b43err(dev->wl, "Radio recalibration timeout\n"); in b43_radio_2056_rcal()
1334 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1335 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT); in b43_radio_2056_rcal()
1336 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); in b43_radio_2056_rcal()
1338 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2); in b43_radio_2056_rcal()
1343 static void b43_radio_init2056_pre(struct b43_wldev *dev) in b43_radio_init2056_pre() argument
1345 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1348 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1350 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1352 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1356 static void b43_radio_init2056_post(struct b43_wldev *dev) in b43_radio_init2056_post() argument
1358 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); in b43_radio_init2056_post()
1359 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); in b43_radio_init2056_post()
1360 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); in b43_radio_init2056_post()
1362 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); in b43_radio_init2056_post()
1363 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); in b43_radio_init2056_post()
1364 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); in b43_radio_init2056_post()
1365 if (dev->phy.do_full_init) in b43_radio_init2056_post()
1366 b43_radio_2056_rcal(dev); in b43_radio_init2056_post()
1373 static void b43_radio_init2056(struct b43_wldev *dev) in b43_radio_init2056() argument
1375 b43_radio_init2056_pre(dev); in b43_radio_init2056()
1376 b2056_upload_inittabs(dev, 0, 0); in b43_radio_init2056()
1377 b43_radio_init2056_post(dev); in b43_radio_init2056()
1384 static void b43_chantab_radio_upload(struct b43_wldev *dev, in b43_chantab_radio_upload() argument
1387 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); in b43_chantab_radio_upload()
1388 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); in b43_chantab_radio_upload()
1389 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); in b43_chantab_radio_upload()
1390 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); in b43_chantab_radio_upload()
1391 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1393 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); in b43_chantab_radio_upload()
1394 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); in b43_chantab_radio_upload()
1395 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); in b43_chantab_radio_upload()
1396 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); in b43_chantab_radio_upload()
1397 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1399 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); in b43_chantab_radio_upload()
1400 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); in b43_chantab_radio_upload()
1401 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); in b43_chantab_radio_upload()
1402 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); in b43_chantab_radio_upload()
1403 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1405 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); in b43_chantab_radio_upload()
1406 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); in b43_chantab_radio_upload()
1407 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); in b43_chantab_radio_upload()
1408 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); in b43_chantab_radio_upload()
1409 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1411 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); in b43_chantab_radio_upload()
1412 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); in b43_chantab_radio_upload()
1413 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); in b43_chantab_radio_upload()
1414 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); in b43_chantab_radio_upload()
1415 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1417 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); in b43_chantab_radio_upload()
1418 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); in b43_chantab_radio_upload()
1422 static void b43_radio_2055_setup(struct b43_wldev *dev, in b43_radio_2055_setup() argument
1425 B43_WARN_ON(dev->phy.rev >= 3); in b43_radio_2055_setup()
1427 b43_chantab_radio_upload(dev, e); in b43_radio_2055_setup()
1429 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); in b43_radio_2055_setup()
1430 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); in b43_radio_2055_setup()
1431 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_radio_2055_setup()
1432 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); in b43_radio_2055_setup()
1436 static void b43_radio_init2055_pre(struct b43_wldev *dev) in b43_radio_init2055_pre() argument
1438 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1440 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1443 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1447 static void b43_radio_init2055_post(struct b43_wldev *dev) in b43_radio_init2055_post() argument
1449 struct b43_phy_n *nphy = dev->phy.n; in b43_radio_init2055_post()
1450 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_radio_init2055_post()
1454 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM in b43_radio_init2055_post()
1455 && dev->dev->board_type == SSB_BOARD_CB2_4321 in b43_radio_init2055_post()
1456 && dev->dev->board_rev >= 0x41); in b43_radio_init2055_post()
1461 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); in b43_radio_init2055_post()
1463 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1464 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1466 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); in b43_radio_init2055_post()
1467 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); in b43_radio_init2055_post()
1468 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); in b43_radio_init2055_post()
1469 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); in b43_radio_init2055_post()
1470 b43_radio_set(dev, B2055_CAL_MISC, 0x1); in b43_radio_init2055_post()
1472 b43_radio_set(dev, B2055_CAL_MISC, 0x40); in b43_radio_init2055_post()
1473 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) in b43_radio_init2055_post()
1474 b43err(dev->wl, "radio post init timeout\n"); in b43_radio_init2055_post()
1475 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); in b43_radio_init2055_post()
1476 b43_switch_channel(dev, dev->phy.channel); in b43_radio_init2055_post()
1477 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1478 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1479 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1480 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1481 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1482 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1484 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1485 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1487 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1488 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1497 static void b43_radio_init2055(struct b43_wldev *dev) in b43_radio_init2055() argument
1499 b43_radio_init2055_pre(dev); in b43_radio_init2055()
1500 if (b43_status(dev) < B43_STAT_INITIALIZED) { in b43_radio_init2055()
1502 b2055_upload_inittab(dev, 0, 0); in b43_radio_init2055()
1504 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ; in b43_radio_init2055()
1505 b2055_upload_inittab(dev, ghz5, 0); in b43_radio_init2055()
1507 b43_radio_init2055_post(dev); in b43_radio_init2055()
1515 static int b43_nphy_load_samples(struct b43_wldev *dev, in b43_nphy_load_samples() argument
1517 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_load_samples()
1523 b43err(dev->wl, "allocation for samples loading failed\n"); in b43_nphy_load_samples()
1527 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_load_samples()
1533 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); in b43_nphy_load_samples()
1537 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_load_samples()
1542 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, in b43_nphy_gen_load_samples() argument
1549 bw = b43_is_40mhz(dev) ? 40 : 20; in b43_nphy_gen_load_samples()
1553 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) in b43_nphy_gen_load_samples()
1558 if (b43_is_40mhz(dev)) in b43_nphy_gen_load_samples()
1566 b43err(dev->wl, "allocation for samples generation failed\n"); in b43_nphy_gen_load_samples()
1579 i = b43_nphy_load_samples(dev, samples, len); in b43_nphy_gen_load_samples()
1585 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, in b43_nphy_run_samples() argument
1589 struct b43_phy *phy = &dev->phy; in b43_nphy_run_samples()
1590 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_run_samples()
1595 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_run_samples()
1600 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; in b43_nphy_run_samples()
1601 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; in b43_nphy_run_samples()
1606 u16 value = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_run_samples()
1608 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, in b43_nphy_run_samples()
1611 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, in b43_nphy_run_samples()
1618 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); in b43_nphy_run_samples()
1623 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; in b43_nphy_run_samples()
1624 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); in b43_nphy_run_samples()
1627 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); in b43_nphy_run_samples()
1630 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); in b43_nphy_run_samples()
1632 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); in b43_nphy_run_samples()
1634 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); in b43_nphy_run_samples()
1636 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); in b43_nphy_run_samples()
1638 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); in b43_nphy_run_samples()
1640 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_run_samples()
1641 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); in b43_nphy_run_samples()
1644 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp); in b43_nphy_run_samples()
1647 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) { in b43_nphy_run_samples()
1654 b43err(dev->wl, "run samples timeout\n"); in b43_nphy_run_samples()
1656 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); in b43_nphy_run_samples()
1658 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_run_samples()
1666 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, in b43_nphy_scale_offset_rssi() argument
1681 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1683 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1685 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1687 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1691 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1693 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1695 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1697 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1701 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1703 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1705 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1707 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1711 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); in b43_nphy_scale_offset_rssi()
1713 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); in b43_nphy_scale_offset_rssi()
1715 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); in b43_nphy_scale_offset_rssi()
1717 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); in b43_nphy_scale_offset_rssi()
1721 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1723 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1725 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1727 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1731 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1733 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1737 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1739 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1744 static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code, in b43_nphy_rssi_select_rev19() argument
1750 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rev3_rssi_select() argument
1757 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); in b43_nphy_rev3_rssi_select()
1758 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); in b43_nphy_rev3_rssi_select()
1759 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); in b43_nphy_rev3_rssi_select()
1760 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); in b43_nphy_rev3_rssi_select()
1761 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); in b43_nphy_rev3_rssi_select()
1762 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); in b43_nphy_rev3_rssi_select()
1763 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); in b43_nphy_rev3_rssi_select()
1764 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); in b43_nphy_rev3_rssi_select()
1772 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); in b43_nphy_rev3_rssi_select()
1780 b43_phy_maskset(dev, reg, 0xFCFF, 0); in b43_nphy_rev3_rssi_select()
1785 b43_phy_maskset(dev, reg, 0xFFC3, 0); in b43_nphy_rev3_rssi_select()
1788 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; in b43_nphy_rev3_rssi_select()
1793 b43_phy_set(dev, reg, val); in b43_nphy_rev3_rssi_select()
1798 b43_phy_set(dev, reg, 0x0020); in b43_nphy_rev3_rssi_select()
1811 b43_phy_maskset(dev, reg, 0xFCFF, val); in b43_nphy_rev3_rssi_select()
1812 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); in b43_nphy_rev3_rssi_select()
1817 b43_current_band(dev->wl); in b43_nphy_rev3_rssi_select()
1819 if (dev->phy.rev < 7) { in b43_nphy_rev3_rssi_select()
1820 if (b43_nphy_ipa(dev)) in b43_nphy_rev3_rssi_select()
1826 b43_radio_write(dev, reg, val); in b43_nphy_rev3_rssi_select()
1832 b43_phy_set(dev, reg, 0x0200); in b43_nphy_rev3_rssi_select()
1839 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rev2_rssi_select() argument
1863 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1864 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1867 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, in b43_nphy_rev2_rssi_select()
1869 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, in b43_nphy_rev2_rssi_select()
1874 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); in b43_nphy_rev2_rssi_select()
1876 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1879 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rev2_rssi_select()
1884 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1887 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1890 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); in b43_nphy_rev2_rssi_select()
1892 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1897 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rev2_rssi_select()
1902 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1905 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1911 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rssi_select() argument
1914 if (dev->phy.rev >= 19) in b43_nphy_rssi_select()
1915 b43_nphy_rssi_select_rev19(dev, code, type); in b43_nphy_rssi_select()
1916 else if (dev->phy.rev >= 3) in b43_nphy_rssi_select()
1917 b43_nphy_rev3_rssi_select(dev, code, type); in b43_nphy_rssi_select()
1919 b43_nphy_rev2_rssi_select(dev, code, type); in b43_nphy_rssi_select()
1923 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, in b43_nphy_set_rssi_2055_vcm() argument
1930 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, in b43_nphy_set_rssi_2055_vcm()
1932 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1935 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, in b43_nphy_set_rssi_2055_vcm()
1937 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1942 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1945 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1952 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type, in b43_nphy_poll_rssi() argument
1962 if (dev->phy.rev >= 3) { in b43_nphy_poll_rssi()
1963 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1964 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_poll_rssi()
1965 save_regs_phy[2] = b43_phy_read(dev, in b43_nphy_poll_rssi()
1967 save_regs_phy[3] = b43_phy_read(dev, in b43_nphy_poll_rssi()
1969 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); in b43_nphy_poll_rssi()
1970 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_poll_rssi()
1971 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); in b43_nphy_poll_rssi()
1972 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); in b43_nphy_poll_rssi()
1975 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1976 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_poll_rssi()
1977 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_poll_rssi()
1978 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); in b43_nphy_poll_rssi()
1979 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); in b43_nphy_poll_rssi()
1980 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); in b43_nphy_poll_rssi()
1981 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); in b43_nphy_poll_rssi()
1986 b43_nphy_rssi_select(dev, 5, rssi_type); in b43_nphy_poll_rssi()
1988 if (dev->phy.rev < 2) { in b43_nphy_poll_rssi()
1989 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); in b43_nphy_poll_rssi()
1990 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); in b43_nphy_poll_rssi()
1997 if (dev->phy.rev < 2) { in b43_nphy_poll_rssi()
1998 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); in b43_nphy_poll_rssi()
1999 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); in b43_nphy_poll_rssi()
2001 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); in b43_nphy_poll_rssi()
2002 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); in b43_nphy_poll_rssi()
2013 if (dev->phy.rev < 2) in b43_nphy_poll_rssi()
2014 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); in b43_nphy_poll_rssi()
2016 if (dev->phy.rev >= 3) { in b43_nphy_poll_rssi()
2017 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2018 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); in b43_nphy_poll_rssi()
2019 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, in b43_nphy_poll_rssi()
2021 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, in b43_nphy_poll_rssi()
2023 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); in b43_nphy_poll_rssi()
2024 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); in b43_nphy_poll_rssi()
2025 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); in b43_nphy_poll_rssi()
2026 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); in b43_nphy_poll_rssi()
2028 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2029 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); in b43_nphy_poll_rssi()
2030 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); in b43_nphy_poll_rssi()
2031 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); in b43_nphy_poll_rssi()
2032 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); in b43_nphy_poll_rssi()
2033 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); in b43_nphy_poll_rssi()
2034 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); in b43_nphy_poll_rssi()
2041 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) in b43_nphy_rev3_rssi_cal() argument
2043 struct b43_phy *phy = &dev->phy; in b43_nphy_rev3_rssi_cal()
2044 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_rev3_rssi_cal()
2092 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2101 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev3_rssi_cal()
2102 b43_nphy_classifier(dev, 7, 4); in b43_nphy_rev3_rssi_cal()
2103 b43_nphy_read_clip_detection(dev, clip_state); in b43_nphy_rev3_rssi_cal()
2104 b43_nphy_write_clip_detection(dev, clip_off); in b43_nphy_rev3_rssi_cal()
2106 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev3_rssi_cal()
2107 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_rev3_rssi_cal()
2109 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); in b43_nphy_rev3_rssi_cal()
2111 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); in b43_nphy_rev3_rssi_cal()
2112 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); in b43_nphy_rev3_rssi_cal()
2114 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2115 b43_nphy_rf_ctl_override_one_to_many(dev, in b43_nphy_rev3_rssi_cal()
2118 b43_nphy_rf_ctl_override_one_to_many(dev, in b43_nphy_rev3_rssi_cal()
2121 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2122 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2123 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rev3_rssi_cal()
2124 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2126 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2129 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2131 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2135 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2136 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2137 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2138 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2139 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_rev3_rssi_cal()
2140 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2141 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2143 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2144 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2148 rx_core_state = b43_nphy_get_rx_core_state(dev); in b43_nphy_rev3_rssi_cal()
2153 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, in b43_nphy_rev3_rssi_cal()
2155 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, in b43_nphy_rev3_rssi_cal()
2160 if (dev->phy.rev >= 7) in b43_nphy_rev3_rssi_cal()
2161 b43_radio_maskset(dev, in b43_nphy_rev3_rssi_cal()
2166 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, in b43_nphy_rev3_rssi_cal()
2168 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8); in b43_nphy_rev3_rssi_cal()
2194 if (dev->phy.rev >= 7) in b43_nphy_rev3_rssi_cal()
2195 b43_radio_maskset(dev, in b43_nphy_rev3_rssi_cal()
2200 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, in b43_nphy_rev3_rssi_cal()
2213 b43_nphy_scale_offset_rssi(dev, 0, offset[i], in b43_nphy_rev3_rssi_cal()
2224 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2226 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2228 b43_nphy_poll_rssi(dev, i, poll_results, 8); in b43_nphy_rev3_rssi_cal()
2236 b43_nphy_scale_offset_rssi(dev, 0, in b43_nphy_rev3_rssi_cal()
2243 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); in b43_nphy_rev3_rssi_cal()
2244 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); in b43_nphy_rev3_rssi_cal()
2246 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev3_rssi_cal()
2248 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); in b43_nphy_rev3_rssi_cal()
2249 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START); in b43_nphy_rev3_rssi_cal()
2250 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); in b43_nphy_rev3_rssi_cal()
2252 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rev3_rssi_cal()
2253 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX); in b43_nphy_rev3_rssi_cal()
2254 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev3_rssi_cal()
2257 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]); in b43_nphy_rev3_rssi_cal()
2260 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_rev3_rssi_cal()
2267 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2268 rssical_radio_regs[0] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2270 rssical_radio_regs[1] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2273 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | in b43_nphy_rev3_rssi_cal()
2275 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 | in b43_nphy_rev3_rssi_cal()
2278 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2279 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2280 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2281 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2282 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X); in b43_nphy_rev3_rssi_cal()
2283 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X); in b43_nphy_rev3_rssi_cal()
2284 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X); in b43_nphy_rev3_rssi_cal()
2285 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X); in b43_nphy_rev3_rssi_cal()
2286 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2287 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2288 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2289 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2292 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_rev3_rssi_cal()
2298 b43_nphy_classifier(dev, 7, class); in b43_nphy_rev3_rssi_cal()
2299 b43_nphy_write_clip_detection(dev, clip_state); in b43_nphy_rev3_rssi_cal()
2303 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type) in b43_nphy_rev2_rssi_cal() argument
2334 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev2_rssi_cal()
2335 b43_nphy_classifier(dev, 7, 4); in b43_nphy_rev2_rssi_cal()
2336 b43_nphy_read_clip_detection(dev, clip_state); in b43_nphy_rev2_rssi_cal()
2337 b43_nphy_write_clip_detection(dev, clip_off); in b43_nphy_rev2_rssi_cal()
2339 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) in b43_nphy_rev2_rssi_cal()
2344 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev2_rssi_cal()
2345 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2346 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); in b43_nphy_rev2_rssi_cal()
2347 b43_radio_write(dev, B2055_C1_PD_RXTX, val); in b43_nphy_rev2_rssi_cal()
2349 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_rev2_rssi_cal()
2350 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2351 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); in b43_nphy_rev2_rssi_cal()
2352 b43_radio_write(dev, B2055_C2_PD_RXTX, val); in b43_nphy_rev2_rssi_cal()
2354 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2355 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2356 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2357 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2358 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2359 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2361 b43_nphy_rssi_select(dev, 5, type); in b43_nphy_rev2_rssi_cal()
2362 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); in b43_nphy_rev2_rssi_cal()
2363 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); in b43_nphy_rev2_rssi_cal()
2370 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); in b43_nphy_rev2_rssi_cal()
2371 b43_nphy_poll_rssi(dev, type, results[vcm], 8); in b43_nphy_rev2_rssi_cal()
2402 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); in b43_nphy_rev2_rssi_cal()
2418 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, in b43_nphy_rev2_rssi_cal()
2422 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); in b43_nphy_rev2_rssi_cal()
2423 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); in b43_nphy_rev2_rssi_cal()
2427 b43_nphy_rssi_select(dev, 1, N_RSSI_NB); in b43_nphy_rev2_rssi_cal()
2430 b43_nphy_rssi_select(dev, 1, N_RSSI_W1); in b43_nphy_rev2_rssi_cal()
2433 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2436 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2442 b43_nphy_rssi_select(dev, 2, N_RSSI_NB); in b43_nphy_rev2_rssi_cal()
2445 b43_nphy_rssi_select(dev, 2, N_RSSI_W1); in b43_nphy_rev2_rssi_cal()
2448 b43_nphy_rssi_select(dev, 2, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2452 b43_nphy_rssi_select(dev, 0, type); in b43_nphy_rev2_rssi_cal()
2454 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); in b43_nphy_rev2_rssi_cal()
2455 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); in b43_nphy_rev2_rssi_cal()
2456 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); in b43_nphy_rev2_rssi_cal()
2457 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); in b43_nphy_rev2_rssi_cal()
2459 b43_nphy_classifier(dev, 7, class); in b43_nphy_rev2_rssi_cal()
2460 b43_nphy_write_clip_detection(dev, clip_state); in b43_nphy_rev2_rssi_cal()
2463 b43_nphy_reset_cca(dev); in b43_nphy_rev2_rssi_cal()
2470 static void b43_nphy_rssi_cal(struct b43_wldev *dev) in b43_nphy_rssi_cal() argument
2472 if (dev->phy.rev >= 19) { in b43_nphy_rssi_cal()
2474 } else if (dev->phy.rev >= 3) { in b43_nphy_rssi_cal()
2475 b43_nphy_rev3_rssi_cal(dev); in b43_nphy_rssi_cal()
2477 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); in b43_nphy_rssi_cal()
2478 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); in b43_nphy_rssi_cal()
2479 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); in b43_nphy_rssi_cal()
2487 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev19() argument
2492 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev7() argument
2494 struct b43_phy *phy = &dev->phy; in b43_nphy_gain_ctl_workarounds_rev7()
2501 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev3() argument
2503 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_gain_ctl_workarounds_rev3()
2513 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL) in b43_nphy_gain_ctl_workarounds_rev3()
2517 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna); in b43_nphy_gain_ctl_workarounds_rev3()
2518 if (ghz5 && dev->phy.rev >= 5) in b43_nphy_gain_ctl_workarounds_rev3()
2523 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); in b43_nphy_gain_ctl_workarounds_rev3()
2526 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev3()
2527 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev3()
2529 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2531 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2533 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2534 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2535 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2536 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2537 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN, in b43_nphy_gain_ctl_workarounds_rev3()
2539 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN, in b43_nphy_gain_ctl_workarounds_rev3()
2541 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2543 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2545 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2546 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2548 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2549 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2550 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2551 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2552 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2553 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2554 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2555 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2556 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2557 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2558 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2559 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2561 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2562 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2564 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, in b43_nphy_gain_ctl_workarounds_rev3()
2567 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2568 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2569 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2570 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2571 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2572 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2574 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); in b43_nphy_gain_ctl_workarounds_rev3()
2575 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); in b43_nphy_gain_ctl_workarounds_rev3()
2576 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); in b43_nphy_gain_ctl_workarounds_rev3()
2577 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); in b43_nphy_gain_ctl_workarounds_rev3()
2578 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); in b43_nphy_gain_ctl_workarounds_rev3()
2579 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev3()
2581 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev3()
2583 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev3()
2586 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev1_2() argument
2588 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_gain_ctl_workarounds_rev1_2()
2597 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2598 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2601 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2602 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2604 if (!b43_is_40mhz(dev)) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2606 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2607 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2608 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2609 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2613 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev1_2()
2615 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev1_2()
2618 if (!b43_is_40mhz(dev)) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2619 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2621 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2623 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2625 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2629 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev1_2()
2632 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && in b43_nphy_gain_ctl_workarounds_rev1_2()
2633 b43_is_40mhz(dev)) in b43_nphy_gain_ctl_workarounds_rev1_2()
2638 code = b43_is_40mhz(dev) ? 6 : 7; in b43_nphy_gain_ctl_workarounds_rev1_2()
2642 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2, in b43_nphy_gain_ctl_workarounds_rev1_2()
2644 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2, in b43_nphy_gain_ctl_workarounds_rev1_2()
2647 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2650 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); in b43_nphy_gain_ctl_workarounds_rev1_2()
2652 b43_nphy_adjust_lna_gain_table(dev); in b43_nphy_gain_ctl_workarounds_rev1_2()
2655 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); in b43_nphy_gain_ctl_workarounds_rev1_2()
2656 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2657 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2658 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2659 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2661 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); in b43_nphy_gain_ctl_workarounds_rev1_2()
2662 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2663 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2664 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2665 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2667 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2670 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_gain_ctl_workarounds_rev1_2()
2674 if (dev->phy.rev == 2) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2676 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_gain_ctl_workarounds_rev1_2()
2680 b43_phy_write(dev, in b43_nphy_gain_ctl_workarounds_rev1_2()
2686 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); in b43_nphy_gain_ctl_workarounds_rev1_2()
2687 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, in b43_nphy_gain_ctl_workarounds_rev1_2()
2691 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_gain_ctl_workarounds_rev1_2()
2692 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); in b43_nphy_gain_ctl_workarounds_rev1_2()
2696 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds() argument
2698 if (dev->phy.rev >= 19) in b43_nphy_gain_ctl_workarounds()
2699 b43_nphy_gain_ctl_workarounds_rev19(dev); in b43_nphy_gain_ctl_workarounds()
2700 else if (dev->phy.rev >= 7) in b43_nphy_gain_ctl_workarounds()
2701 b43_nphy_gain_ctl_workarounds_rev7(dev); in b43_nphy_gain_ctl_workarounds()
2702 else if (dev->phy.rev >= 3) in b43_nphy_gain_ctl_workarounds()
2703 b43_nphy_gain_ctl_workarounds_rev3(dev); in b43_nphy_gain_ctl_workarounds()
2705 b43_nphy_gain_ctl_workarounds_rev1_2(dev); in b43_nphy_gain_ctl_workarounds()
2708 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) in b43_nphy_workarounds_rev7plus() argument
2710 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev7plus()
2711 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds_rev7plus()
2739 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev7plus()
2740 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); in b43_nphy_workarounds_rev7plus()
2741 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev7plus()
2742 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); in b43_nphy_workarounds_rev7plus()
2743 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); in b43_nphy_workarounds_rev7plus()
2744 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev7plus()
2747 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); in b43_nphy_workarounds_rev7plus()
2748 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); in b43_nphy_workarounds_rev7plus()
2749 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); in b43_nphy_workarounds_rev7plus()
2750 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); in b43_nphy_workarounds_rev7plus()
2751 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); in b43_nphy_workarounds_rev7plus()
2752 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); in b43_nphy_workarounds_rev7plus()
2753 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); in b43_nphy_workarounds_rev7plus()
2754 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); in b43_nphy_workarounds_rev7plus()
2755 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); in b43_nphy_workarounds_rev7plus()
2756 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); in b43_nphy_workarounds_rev7plus()
2757 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); in b43_nphy_workarounds_rev7plus()
2758 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2759 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2760 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2761 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2762 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2763 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2767 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); in b43_nphy_workarounds_rev7plus()
2768 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); in b43_nphy_workarounds_rev7plus()
2770 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); in b43_nphy_workarounds_rev7plus()
2771 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); in b43_nphy_workarounds_rev7plus()
2775 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); in b43_nphy_workarounds_rev7plus()
2777 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); in b43_nphy_workarounds_rev7plus()
2779 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); in b43_nphy_workarounds_rev7plus()
2780 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); in b43_nphy_workarounds_rev7plus()
2781 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev7plus()
2783 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev7plus()
2784 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2785 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2787 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, in b43_nphy_workarounds_rev7plus()
2789 if (b43_nphy_ipa(dev)) in b43_nphy_workarounds_rev7plus()
2790 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev7plus()
2793 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2794 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2797 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2798 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2799 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2802 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL); in b43_nphy_workarounds_rev7plus()
2803 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL); in b43_nphy_workarounds_rev7plus()
2805 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev7plus()
2806 bool ghz2 = b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ; in b43_nphy_workarounds_rev7plus()
2811 if (phy->rev == 8 && b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev7plus()
2834 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2945 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), in b43_nphy_workarounds_rev7plus()
2947 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), in b43_nphy_workarounds_rev7plus()
2949 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), in b43_nphy_workarounds_rev7plus()
2951 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), in b43_nphy_workarounds_rev7plus()
2953 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), in b43_nphy_workarounds_rev7plus()
2955 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), in b43_nphy_workarounds_rev7plus()
2957 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), in b43_nphy_workarounds_rev7plus()
2959 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), in b43_nphy_workarounds_rev7plus()
2964 b43_phy_write(dev, 0x32F, 0x3); in b43_nphy_workarounds_rev7plus()
2967 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); in b43_nphy_workarounds_rev7plus()
2972 b43_radio_write(dev, 0x5, 0x05); in b43_nphy_workarounds_rev7plus()
2973 b43_radio_write(dev, 0x6, 0x30); in b43_nphy_workarounds_rev7plus()
2974 b43_radio_write(dev, 0x7, 0x00); in b43_nphy_workarounds_rev7plus()
2975 b43_radio_set(dev, 0x4f, 0x1); in b43_nphy_workarounds_rev7plus()
2976 b43_radio_set(dev, 0xd4, 0x1); in b43_nphy_workarounds_rev7plus()
2985 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2988 b43_radio_write(dev, 0x5F, bias); in b43_nphy_workarounds_rev7plus()
2989 b43_radio_write(dev, 0x64, conv); in b43_nphy_workarounds_rev7plus()
2990 b43_radio_write(dev, 0x66, filt); in b43_nphy_workarounds_rev7plus()
2992 b43_radio_write(dev, 0xE8, bias); in b43_nphy_workarounds_rev7plus()
2993 b43_radio_write(dev, 0xE9, conv); in b43_nphy_workarounds_rev7plus()
2994 b43_radio_write(dev, 0xEB, filt); in b43_nphy_workarounds_rev7plus()
3000 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev7plus()
3001 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
3006 b43_radio_write(dev, 0x51, in b43_nphy_workarounds_rev7plus()
3009 b43_radio_write(dev, 0xd6, in b43_nphy_workarounds_rev7plus()
3017 b43_radio_write(dev, 0x64, in b43_nphy_workarounds_rev7plus()
3019 b43_radio_write(dev, 0x5F, in b43_nphy_workarounds_rev7plus()
3021 b43_radio_write(dev, 0x66, in b43_nphy_workarounds_rev7plus()
3023 b43_radio_write(dev, 0x59, in b43_nphy_workarounds_rev7plus()
3025 b43_radio_write(dev, 0x80, in b43_nphy_workarounds_rev7plus()
3028 b43_radio_write(dev, 0x69, in b43_nphy_workarounds_rev7plus()
3030 b43_radio_write(dev, 0xE8, in b43_nphy_workarounds_rev7plus()
3032 b43_radio_write(dev, 0xEB, in b43_nphy_workarounds_rev7plus()
3034 b43_radio_write(dev, 0xDE, in b43_nphy_workarounds_rev7plus()
3036 b43_radio_write(dev, 0x105, in b43_nphy_workarounds_rev7plus()
3043 if (!b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev7plus()
3044 b43_radio_write(dev, 0x5F, 0x14); in b43_nphy_workarounds_rev7plus()
3045 b43_radio_write(dev, 0xE8, 0x12); in b43_nphy_workarounds_rev7plus()
3047 b43_radio_write(dev, 0x5F, 0x16); in b43_nphy_workarounds_rev7plus()
3048 b43_radio_write(dev, 0xE8, 0x16); in b43_nphy_workarounds_rev7plus()
3055 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); in b43_nphy_workarounds_rev7plus()
3056 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); in b43_nphy_workarounds_rev7plus()
3057 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); in b43_nphy_workarounds_rev7plus()
3058 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); in b43_nphy_workarounds_rev7plus()
3059 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); in b43_nphy_workarounds_rev7plus()
3060 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); in b43_nphy_workarounds_rev7plus()
3061 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); in b43_nphy_workarounds_rev7plus()
3062 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); in b43_nphy_workarounds_rev7plus()
3070 b43_radio_write(dev, 0x7D, 0xFF); in b43_nphy_workarounds_rev7plus()
3071 b43_radio_write(dev, 0xFE, 0xFF); in b43_nphy_workarounds_rev7plus()
3078 b43_radio_write(dev, 0x5c, 0x61); in b43_nphy_workarounds_rev7plus()
3079 b43_radio_write(dev, 0x51, 0x70); in b43_nphy_workarounds_rev7plus()
3081 b43_radio_write(dev, 0xe1, 0x61); in b43_nphy_workarounds_rev7plus()
3082 b43_radio_write(dev, 0xd6, 0x70); in b43_nphy_workarounds_rev7plus()
3089 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); in b43_nphy_workarounds_rev7plus()
3090 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); in b43_nphy_workarounds_rev7plus()
3093 b43_radio_write(dev, 0x1a1, 0x00); in b43_nphy_workarounds_rev7plus()
3094 b43_radio_write(dev, 0x1a2, 0x3f); in b43_nphy_workarounds_rev7plus()
3095 b43_radio_write(dev, 0x1a6, 0x3f); in b43_nphy_workarounds_rev7plus()
3097 b43_radio_write(dev, 0x1a7, 0x00); in b43_nphy_workarounds_rev7plus()
3098 b43_radio_write(dev, 0x1ab, 0x3f); in b43_nphy_workarounds_rev7plus()
3099 b43_radio_write(dev, 0x1ac, 0x3f); in b43_nphy_workarounds_rev7plus()
3103 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); in b43_nphy_workarounds_rev7plus()
3104 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); in b43_nphy_workarounds_rev7plus()
3105 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); in b43_nphy_workarounds_rev7plus()
3106 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); in b43_nphy_workarounds_rev7plus()
3108 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); in b43_nphy_workarounds_rev7plus()
3109 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); in b43_nphy_workarounds_rev7plus()
3110 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); in b43_nphy_workarounds_rev7plus()
3111 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); in b43_nphy_workarounds_rev7plus()
3112 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); in b43_nphy_workarounds_rev7plus()
3113 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); in b43_nphy_workarounds_rev7plus()
3115 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); in b43_nphy_workarounds_rev7plus()
3116 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); in b43_nphy_workarounds_rev7plus()
3117 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); in b43_nphy_workarounds_rev7plus()
3118 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); in b43_nphy_workarounds_rev7plus()
3121 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); in b43_nphy_workarounds_rev7plus()
3123 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); in b43_nphy_workarounds_rev7plus()
3124 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3125 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); in b43_nphy_workarounds_rev7plus()
3126 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); in b43_nphy_workarounds_rev7plus()
3127 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3128 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); in b43_nphy_workarounds_rev7plus()
3129 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); in b43_nphy_workarounds_rev7plus()
3131 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3132 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3133 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3135 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3136 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3137 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3139 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev7plus()
3153 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) in b43_nphy_workarounds_rev3plus() argument
3155 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_workarounds_rev3plus()
3156 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev3plus()
3188 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); in b43_nphy_workarounds_rev3plus()
3189 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); in b43_nphy_workarounds_rev3plus()
3191 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev3plus()
3193 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev3plus()
3195 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev3plus()
3196 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); in b43_nphy_workarounds_rev3plus()
3197 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev3plus()
3198 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); in b43_nphy_workarounds_rev3plus()
3199 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); in b43_nphy_workarounds_rev3plus()
3200 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev3plus()
3202 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3203 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3206 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, in b43_nphy_workarounds_rev3plus()
3210 if (b43_nphy_ipa(dev)) in b43_nphy_workarounds_rev3plus()
3211 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev3plus()
3215 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev3plus()
3220 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, in b43_nphy_workarounds_rev3plus()
3224 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? in b43_nphy_workarounds_rev3plus()
3226 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); in b43_nphy_workarounds_rev3plus()
3228 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); in b43_nphy_workarounds_rev3plus()
3230 if (!b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev3plus()
3231 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); in b43_nphy_workarounds_rev3plus()
3232 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); in b43_nphy_workarounds_rev3plus()
3234 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); in b43_nphy_workarounds_rev3plus()
3235 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); in b43_nphy_workarounds_rev3plus()
3238 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev3plus()
3240 b43_ntab_write(dev, B43_NTAB16(8, 0), 2); in b43_nphy_workarounds_rev3plus()
3241 b43_ntab_write(dev, B43_NTAB16(8, 16), 2); in b43_nphy_workarounds_rev3plus()
3243 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_workarounds_rev3plus()
3251 if (!(dev->phy.rev >= 4 && in b43_nphy_workarounds_rev3plus()
3252 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) in b43_nphy_workarounds_rev3plus()
3257 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3258 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3259 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3260 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3263 if (dev->phy.rev >= 6) { in b43_nphy_workarounds_rev3plus()
3264 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_workarounds_rev3plus()
3269 } else if (dev->phy.rev == 5) { in b43_nphy_workarounds_rev3plus()
3273 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3274 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3275 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3276 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3280 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) { in b43_nphy_workarounds_rev3plus()
3301 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3302 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3304 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3305 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3309 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3310 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3311 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3312 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3313 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3314 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3315 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3316 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3317 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3318 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3319 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3320 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3325 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || in b43_nphy_workarounds_rev3plus()
3327 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) in b43_nphy_workarounds_rev3plus()
3331 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); in b43_nphy_workarounds_rev3plus()
3332 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); in b43_nphy_workarounds_rev3plus()
3333 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); in b43_nphy_workarounds_rev3plus()
3335 if (dev->phy.rev == 4 && in b43_nphy_workarounds_rev3plus()
3336 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_workarounds_rev3plus()
3337 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, in b43_nphy_workarounds_rev3plus()
3339 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, in b43_nphy_workarounds_rev3plus()
3344 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); in b43_nphy_workarounds_rev3plus()
3345 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); in b43_nphy_workarounds_rev3plus()
3346 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); in b43_nphy_workarounds_rev3plus()
3347 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); in b43_nphy_workarounds_rev3plus()
3348 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3349 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3350 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3351 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3352 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3353 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3354 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3355 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3357 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) in b43_nphy_workarounds_rev3plus()
3361 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) in b43_nphy_workarounds_rev1_2() argument
3363 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev1_2()
3364 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds_rev1_2()
3374 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) { in b43_nphy_workarounds_rev1_2()
3379 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && in b43_nphy_workarounds_rev1_2()
3381 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3382 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3384 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3385 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3388 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); in b43_nphy_workarounds_rev1_2()
3389 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); in b43_nphy_workarounds_rev1_2()
3390 if (dev->phy.rev < 3) { in b43_nphy_workarounds_rev1_2()
3391 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3392 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3395 if (dev->phy.rev < 2) { in b43_nphy_workarounds_rev1_2()
3396 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); in b43_nphy_workarounds_rev1_2()
3397 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); in b43_nphy_workarounds_rev1_2()
3398 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3399 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3400 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); in b43_nphy_workarounds_rev1_2()
3401 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); in b43_nphy_workarounds_rev1_2()
3404 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_workarounds_rev1_2()
3405 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_workarounds_rev1_2()
3406 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_workarounds_rev1_2()
3407 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_workarounds_rev1_2()
3409 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); in b43_nphy_workarounds_rev1_2()
3410 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); in b43_nphy_workarounds_rev1_2()
3412 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev1_2()
3414 if (dev->phy.rev < 2) { in b43_nphy_workarounds_rev1_2()
3415 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) in b43_nphy_workarounds_rev1_2()
3416 b43_hf_write(dev, b43_hf_read(dev) | in b43_nphy_workarounds_rev1_2()
3418 } else if (dev->phy.rev == 2) { in b43_nphy_workarounds_rev1_2()
3419 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); in b43_nphy_workarounds_rev1_2()
3420 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); in b43_nphy_workarounds_rev1_2()
3423 if (dev->phy.rev < 2) in b43_nphy_workarounds_rev1_2()
3424 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, in b43_nphy_workarounds_rev1_2()
3428 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); in b43_nphy_workarounds_rev1_2()
3429 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); in b43_nphy_workarounds_rev1_2()
3430 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); in b43_nphy_workarounds_rev1_2()
3431 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); in b43_nphy_workarounds_rev1_2()
3432 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); in b43_nphy_workarounds_rev1_2()
3433 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); in b43_nphy_workarounds_rev1_2()
3435 if (dev->phy.rev < 3) { in b43_nphy_workarounds_rev1_2()
3436 b43_phy_mask(dev, B43_NPHY_PIL_DW1, in b43_nphy_workarounds_rev1_2()
3438 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); in b43_nphy_workarounds_rev1_2()
3439 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); in b43_nphy_workarounds_rev1_2()
3440 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); in b43_nphy_workarounds_rev1_2()
3443 if (dev->phy.rev == 2) in b43_nphy_workarounds_rev1_2()
3444 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, in b43_nphy_workarounds_rev1_2()
3449 static void b43_nphy_workarounds(struct b43_wldev *dev) in b43_nphy_workarounds() argument
3451 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds()
3454 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) in b43_nphy_workarounds()
3455 b43_nphy_classifier(dev, 1, 0); in b43_nphy_workarounds()
3457 b43_nphy_classifier(dev, 1, 1); in b43_nphy_workarounds()
3460 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_workarounds()
3462 b43_phy_set(dev, B43_NPHY_IQFLIP, in b43_nphy_workarounds()
3466 if (dev->phy.rev >= 7) in b43_nphy_workarounds()
3467 b43_nphy_workarounds_rev7plus(dev); in b43_nphy_workarounds()
3468 else if (dev->phy.rev >= 3) in b43_nphy_workarounds()
3469 b43_nphy_workarounds_rev3plus(dev); in b43_nphy_workarounds()
3471 b43_nphy_workarounds_rev1_2(dev); in b43_nphy_workarounds()
3474 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_workarounds()
3485 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, in b43_nphy_tx_tone() argument
3488 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); in b43_nphy_tx_tone()
3491 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, in b43_nphy_tx_tone()
3497 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) in b43_nphy_update_txrx_chain() argument
3499 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_update_txrx_chain()
3512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, in b43_nphy_update_txrx_chain()
3517 b43_phy_set(dev, B43_NPHY_RFSEQMODE, in b43_nphy_update_txrx_chain()
3520 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, in b43_nphy_update_txrx_chain()
3525 static void b43_nphy_stop_playback(struct b43_wldev *dev) in b43_nphy_stop_playback() argument
3527 struct b43_phy *phy = &dev->phy; in b43_nphy_stop_playback()
3528 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_stop_playback()
3532 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_stop_playback()
3534 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); in b43_nphy_stop_playback()
3536 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); in b43_nphy_stop_playback()
3538 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_stop_playback()
3540 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); in b43_nphy_stop_playback()
3544 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); in b43_nphy_stop_playback()
3550 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, in b43_nphy_stop_playback()
3553 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); in b43_nphy_stop_playback()
3558 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_stop_playback()
3562 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, in b43_nphy_iq_cal_gain_params() argument
3566 struct b43_phy *phy = &dev->phy; in b43_nphy_iq_cal_gain_params()
3570 if (dev->phy.rev >= 3) { in b43_nphy_iq_cal_gain_params()
3589 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? in b43_nphy_iq_cal_gain_params()
3611 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) in b43_nphy_tx_power_ctrl() argument
3613 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctrl()
3614 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctrl()
3617 enum ieee80211_band band = b43_current_band(dev->wl); in b43_nphy_tx_power_ctrl()
3620 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_tx_power_ctrl()
3624 if (dev->phy.rev >= 3 && in b43_nphy_tx_power_ctrl()
3625 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & in b43_nphy_tx_power_ctrl()
3630 nphy->tx_pwr_idx[0] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3632 nphy->tx_pwr_idx[1] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3636 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); in b43_nphy_tx_power_ctrl()
3638 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3640 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); in b43_nphy_tx_power_ctrl()
3642 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3645 if (dev->phy.rev >= 3) in b43_nphy_tx_power_ctrl()
3647 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); in b43_nphy_tx_power_ctrl()
3649 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3650 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_ctrl()
3651 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_ctrl()
3653 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_ctrl()
3656 if (dev->phy.rev == 2) in b43_nphy_tx_power_ctrl()
3657 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_nphy_tx_power_ctrl()
3659 else if (dev->phy.rev < 2) in b43_nphy_tx_power_ctrl()
3660 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_nphy_tx_power_ctrl()
3663 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) in b43_nphy_tx_power_ctrl()
3664 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); in b43_nphy_tx_power_ctrl()
3666 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, in b43_nphy_tx_power_ctrl()
3668 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, in b43_nphy_tx_power_ctrl()
3675 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3680 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); in b43_nphy_tx_power_ctrl()
3686 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3689 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctrl()
3693 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3697 b43_phy_maskset(dev, in b43_nphy_tx_power_ctrl()
3704 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3708 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3711 if (dev->phy.rev > 1) in b43_nphy_tx_power_ctrl()
3712 b43_phy_maskset(dev, in b43_nphy_tx_power_ctrl()
3722 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3723 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); in b43_nphy_tx_power_ctrl()
3724 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); in b43_nphy_tx_power_ctrl()
3726 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); in b43_nphy_tx_power_ctrl()
3729 if (dev->phy.rev == 2) in b43_nphy_tx_power_ctrl()
3730 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); in b43_nphy_tx_power_ctrl()
3731 else if (dev->phy.rev < 2) in b43_nphy_tx_power_ctrl()
3732 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); in b43_nphy_tx_power_ctrl()
3734 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) in b43_nphy_tx_power_ctrl()
3735 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); in b43_nphy_tx_power_ctrl()
3737 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_ctrl()
3738 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); in b43_nphy_tx_power_ctrl()
3739 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); in b43_nphy_tx_power_ctrl()
3744 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_ctrl()
3748 static void b43_nphy_tx_power_fix(struct b43_wldev *dev) in b43_nphy_tx_power_fix() argument
3750 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_fix()
3751 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_fix()
3752 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_tx_power_fix()
3761 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_tx_power_fix()
3764 if (dev->phy.rev >= 7) { in b43_nphy_tx_power_fix()
3766 } else if (dev->phy.rev >= 3) { in b43_nphy_tx_power_fix()
3773 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_tx_power_fix()
3790 if (dev->phy.rev < 7 && in b43_nphy_tx_power_fix()
3802 const u32 *table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_tx_power_fix()
3808 if (dev->phy.rev >= 3) in b43_nphy_tx_power_fix()
3813 if (dev->phy.rev >= 7) in b43_nphy_tx_power_fix()
3819 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_fix()
3821 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_fix()
3823 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_fix()
3825 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_fix()
3829 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); in b43_nphy_tx_power_fix()
3831 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); in b43_nphy_tx_power_fix()
3833 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); in b43_nphy_tx_power_fix()
3835 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); in b43_nphy_tx_power_fix()
3840 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); in b43_nphy_tx_power_fix()
3842 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_fix()
3846 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, in b43_nphy_tx_power_fix()
3848 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); in b43_nphy_tx_power_fix()
3849 b43_phy_set(dev, reg, 0x4); in b43_nphy_tx_power_fix()
3853 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); in b43_nphy_tx_power_fix()
3856 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_fix()
3859 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev) in b43_nphy_ipa_internal_tssi_setup() argument
3861 struct b43_phy *phy = &dev->phy; in b43_nphy_ipa_internal_tssi_setup()
3871 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_ipa_internal_tssi_setup()
3872 b43_radio_write(dev, r + 0x5, 0x5); in b43_nphy_ipa_internal_tssi_setup()
3873 b43_radio_write(dev, r + 0x9, 0xE); in b43_nphy_ipa_internal_tssi_setup()
3875 b43_radio_write(dev, r + 0xA, 0); in b43_nphy_ipa_internal_tssi_setup()
3877 b43_radio_write(dev, r + 0xB, 1); in b43_nphy_ipa_internal_tssi_setup()
3879 b43_radio_write(dev, r + 0xB, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3881 b43_radio_write(dev, r + 0x5, 0x9); in b43_nphy_ipa_internal_tssi_setup()
3882 b43_radio_write(dev, r + 0x9, 0xC); in b43_nphy_ipa_internal_tssi_setup()
3883 b43_radio_write(dev, r + 0xB, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3885 b43_radio_write(dev, r + 0xA, 1); in b43_nphy_ipa_internal_tssi_setup()
3887 b43_radio_write(dev, r + 0xA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3889 b43_radio_write(dev, r + 0x6, 0); in b43_nphy_ipa_internal_tssi_setup()
3890 b43_radio_write(dev, r + 0x7, 0); in b43_nphy_ipa_internal_tssi_setup()
3891 b43_radio_write(dev, r + 0x8, 3); in b43_nphy_ipa_internal_tssi_setup()
3892 b43_radio_write(dev, r + 0xC, 0); in b43_nphy_ipa_internal_tssi_setup()
3895 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_ipa_internal_tssi_setup()
3896 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); in b43_nphy_ipa_internal_tssi_setup()
3898 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); in b43_nphy_ipa_internal_tssi_setup()
3899 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); in b43_nphy_ipa_internal_tssi_setup()
3900 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); in b43_nphy_ipa_internal_tssi_setup()
3905 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); in b43_nphy_ipa_internal_tssi_setup()
3906 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); in b43_nphy_ipa_internal_tssi_setup()
3907 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3); in b43_nphy_ipa_internal_tssi_setup()
3908 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); in b43_nphy_ipa_internal_tssi_setup()
3909 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8); in b43_nphy_ipa_internal_tssi_setup()
3910 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); in b43_nphy_ipa_internal_tssi_setup()
3911 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); in b43_nphy_ipa_internal_tssi_setup()
3912 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_ipa_internal_tssi_setup()
3913 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, in b43_nphy_ipa_internal_tssi_setup()
3916 b43_radio_write(dev, r | B2056_TX_TSSIA, in b43_nphy_ipa_internal_tssi_setup()
3919 b43_radio_write(dev, r | B2056_TX_TSSIG, in b43_nphy_ipa_internal_tssi_setup()
3922 b43_radio_write(dev, r | B2056_TX_TSSIG, in b43_nphy_ipa_internal_tssi_setup()
3924 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, in b43_nphy_ipa_internal_tssi_setup()
3927 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, in b43_nphy_ipa_internal_tssi_setup()
3929 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3930 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3931 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, in b43_nphy_ipa_internal_tssi_setup()
3943 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) in b43_nphy_tx_power_ctl_idle_tssi() argument
3945 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctl_idle_tssi()
3946 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctl_idle_tssi()
3954 if (b43_nphy_ipa(dev)) in b43_nphy_tx_power_ctl_idle_tssi()
3955 b43_nphy_ipa_internal_tssi_setup(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3958 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3960 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3962 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); in b43_nphy_tx_power_ctl_idle_tssi()
3964 b43_nphy_stop_playback(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3965 b43_nphy_tx_tone(dev, 4000, 0, false, false, false); in b43_nphy_tx_power_ctl_idle_tssi()
3967 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1); in b43_nphy_tx_power_ctl_idle_tssi()
3968 b43_nphy_stop_playback(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3970 b43_nphy_rssi_select(dev, 0, N_RSSI_W1); in b43_nphy_tx_power_ctl_idle_tssi()
3973 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3975 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3977 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); in b43_nphy_tx_power_ctl_idle_tssi()
3994 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev) in b43_nphy_tx_prepare_adjusted_power_table() argument
3996 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_prepare_adjusted_power_table()
4022 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) { in b43_nphy_tx_prepare_adjusted_power_table()
4026 idx = b43_is_40mhz(dev) ? 52 : 4; in b43_nphy_tx_prepare_adjusted_power_table()
4030 idx = b43_is_40mhz(dev) ? 76 : 28; in b43_nphy_tx_prepare_adjusted_power_table()
4033 idx = b43_is_40mhz(dev) ? 84 : 36; in b43_nphy_tx_prepare_adjusted_power_table()
4036 idx = b43_is_40mhz(dev) ? 92 : 44; in b43_nphy_tx_prepare_adjusted_power_table()
4055 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev) in b43_nphy_tx_power_ctl_setup() argument
4057 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctl_setup()
4058 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctl_setup()
4059 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_tx_power_ctl_setup()
4073 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_tx_power_ctl_setup()
4074 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4075 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_tx_power_ctl_setup()
4080 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_tx_power_ctl_setup()
4082 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN); in b43_nphy_tx_power_ctl_setup()
4083 if (dev->phy.rev >= 3) in b43_nphy_tx_power_ctl_setup()
4084 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4087 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4090 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_tx_power_ctl_setup()
4091 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4101 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_tx_power_ctl_setup()
4143 ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr); in b43_nphy_tx_power_ctl_setup()
4149 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctl_setup()
4151 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); in b43_nphy_tx_power_ctl_setup()
4152 if (dev->phy.rev >= 7) { in b43_nphy_tx_power_ctl_setup()
4155 if (b43_nphy_ipa(dev)) in b43_nphy_tx_power_ctl_setup()
4156 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC); in b43_nphy_tx_power_ctl_setup()
4159 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_ctl_setup()
4160 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; in b43_nphy_tx_power_ctl_setup()
4161 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4163 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4166 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4168 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4174 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_tx_power_ctl_setup()
4175 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4176 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_tx_power_ctl_setup()
4183 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4185 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctl_setup()
4188 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4190 if (dev->phy.rev > 1) in b43_nphy_tx_power_ctl_setup()
4191 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctl_setup()
4195 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_tx_power_ctl_setup()
4196 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4198 b43_phy_write(dev, B43_NPHY_TXPCTL_N, in b43_nphy_tx_power_ctl_setup()
4201 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI, in b43_nphy_tx_power_ctl_setup()
4205 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR, in b43_nphy_tx_power_ctl_setup()
4214 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1))) in b43_nphy_tx_power_ctl_setup()
4218 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); in b43_nphy_tx_power_ctl_setup()
4221 b43_nphy_tx_prepare_adjusted_power_table(dev); in b43_nphy_tx_power_ctl_setup()
4222 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); in b43_nphy_tx_power_ctl_setup()
4223 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); in b43_nphy_tx_power_ctl_setup()
4226 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_tx_power_ctl_setup()
4229 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) in b43_nphy_tx_gain_table_upload() argument
4231 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_gain_table_upload()
4239 table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_tx_gain_table_upload()
4243 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); in b43_nphy_tx_gain_table_upload()
4244 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); in b43_nphy_tx_gain_table_upload()
4256 rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev); in b43_nphy_tx_gain_table_upload()
4270 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_tx_gain_table_upload()
4276 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_tx_gain_table_upload()
4282 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset); in b43_nphy_tx_gain_table_upload()
4283 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset); in b43_nphy_tx_gain_table_upload()
4288 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) in b43_nphy_pa_override() argument
4290 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_pa_override()
4295 nphy->rfctrl_intc1_save = b43_phy_read(dev, in b43_nphy_pa_override()
4297 nphy->rfctrl_intc2_save = b43_phy_read(dev, in b43_nphy_pa_override()
4299 band = b43_current_band(dev->wl); in b43_nphy_pa_override()
4300 if (dev->phy.rev >= 7) { in b43_nphy_pa_override()
4302 } else if (dev->phy.rev >= 3) { in b43_nphy_pa_override()
4313 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); in b43_nphy_pa_override()
4314 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); in b43_nphy_pa_override()
4316 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, in b43_nphy_pa_override()
4318 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, in b43_nphy_pa_override()
4327 static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev) in b43_nphy_tx_lpf_bw() argument
4331 if (dev->phy.rev < 3 || dev->phy.rev >= 7) in b43_nphy_tx_lpf_bw()
4334 if (b43_nphy_ipa(dev)) in b43_nphy_tx_lpf_bw()
4335 tmp = b43_is_40mhz(dev) ? 5 : 4; in b43_nphy_tx_lpf_bw()
4337 tmp = b43_is_40mhz(dev) ? 3 : 1; in b43_nphy_tx_lpf_bw()
4338 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, in b43_nphy_tx_lpf_bw()
4341 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_lpf_bw()
4342 tmp = b43_is_40mhz(dev) ? 4 : 1; in b43_nphy_tx_lpf_bw()
4343 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, in b43_nphy_tx_lpf_bw()
4349 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, in b43_nphy_rx_iq_est() argument
4355 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); in b43_nphy_rx_iq_est()
4356 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); in b43_nphy_rx_iq_est()
4358 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); in b43_nphy_rx_iq_est()
4360 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); in b43_nphy_rx_iq_est()
4362 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); in b43_nphy_rx_iq_est()
4365 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); in b43_nphy_rx_iq_est()
4367 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4368 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); in b43_nphy_rx_iq_est()
4369 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4370 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); in b43_nphy_rx_iq_est()
4371 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4372 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); in b43_nphy_rx_iq_est()
4374 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4375 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); in b43_nphy_rx_iq_est()
4376 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4377 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); in b43_nphy_rx_iq_est()
4378 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4379 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); in b43_nphy_rx_iq_est()
4388 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, in b43_nphy_rx_iq_coeffs() argument
4392 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); in b43_nphy_rx_iq_coeffs()
4393 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); in b43_nphy_rx_iq_coeffs()
4394 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); in b43_nphy_rx_iq_coeffs()
4395 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); in b43_nphy_rx_iq_coeffs()
4397 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); in b43_nphy_rx_iq_coeffs()
4398 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); in b43_nphy_rx_iq_coeffs()
4399 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); in b43_nphy_rx_iq_coeffs()
4400 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); in b43_nphy_rx_iq_coeffs()
4407 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4409 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4411 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4413 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4414 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4416 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4417 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4419 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4420 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4421 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4422 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4423 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4424 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4425 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4426 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4430 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4433 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4435 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4437 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4438 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4440 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4441 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4443 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4444 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4445 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4446 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4447 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4448 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4449 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4450 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4452 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4453 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4455 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4458 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4460 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4462 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4466 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4467 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4469 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4470 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4473 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4474 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4475 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4484 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4486 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4492 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) in b43_nphy_calc_rx_iq_comp() argument
4510 b43_nphy_rx_iq_coeffs(dev, false, &old); in b43_nphy_calc_rx_iq_comp()
4511 b43_nphy_rx_iq_coeffs(dev, true, &new); in b43_nphy_calc_rx_iq_comp()
4512 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); in b43_nphy_calc_rx_iq_comp()
4565 if (dev->phy.rev >= 3) { in b43_nphy_calc_rx_iq_comp()
4573 if (dev->phy.rev >= 3) { in b43_nphy_calc_rx_iq_comp()
4586 b43_nphy_rx_iq_coeffs(dev, true, &new); in b43_nphy_calc_rx_iq_comp()
4590 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) in b43_nphy_tx_iq_workaround() argument
4593 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); in b43_nphy_tx_iq_workaround()
4595 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); in b43_nphy_tx_iq_workaround()
4596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); in b43_nphy_tx_iq_workaround()
4597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); in b43_nphy_tx_iq_workaround()
4598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); in b43_nphy_tx_iq_workaround()
4602 static void b43_nphy_spur_workaround(struct b43_wldev *dev) in b43_nphy_spur_workaround() argument
4604 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_spur_workaround()
4606 u8 channel = dev->phy.channel; in b43_nphy_spur_workaround()
4610 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_spur_workaround()
4613 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_spur_workaround()
4617 if (channel == 11 && b43_is_40mhz(dev)) in b43_nphy_spur_workaround()
4657 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_spur_workaround()
4661 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) in b43_nphy_tx_pwr_ctrl_coef_setup() argument
4663 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_pwr_ctrl_coef_setup()
4671 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_tx_pwr_ctrl_coef_setup()
4673 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); in b43_nphy_tx_pwr_ctrl_coef_setup()
4678 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_tx_pwr_ctrl_coef_setup()
4681 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, in b43_nphy_tx_pwr_ctrl_coef_setup()
4683 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_tx_pwr_ctrl_coef_setup()
4692 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_tx_pwr_ctrl_coef_setup()
4695 if (dev->phy.rev >= 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4702 if (dev->phy.rev < 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4708 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, in b43_nphy_tx_pwr_ctrl_coef_setup()
4710 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_tx_pwr_ctrl_coef_setup()
4715 if (dev->phy.rev >= 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4716 b43_shm_write16(dev, B43_SHM_SHARED, in b43_nphy_tx_pwr_ctrl_coef_setup()
4718 b43_shm_write16(dev, B43_SHM_SHARED, in b43_nphy_tx_pwr_ctrl_coef_setup()
4723 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_tx_pwr_ctrl_coef_setup()
4730 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) in b43_nphy_restore_rssi_cal() argument
4732 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_restore_rssi_cal()
4737 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_restore_rssi_cal()
4749 if (dev->phy.rev >= 19) { in b43_nphy_restore_rssi_cal()
4751 } else if (dev->phy.rev >= 7) { in b43_nphy_restore_rssi_cal()
4752 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, in b43_nphy_restore_rssi_cal()
4754 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, in b43_nphy_restore_rssi_cal()
4757 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4759 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4763 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); in b43_nphy_restore_rssi_cal()
4764 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); in b43_nphy_restore_rssi_cal()
4765 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); in b43_nphy_restore_rssi_cal()
4766 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); in b43_nphy_restore_rssi_cal()
4768 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); in b43_nphy_restore_rssi_cal()
4769 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); in b43_nphy_restore_rssi_cal()
4770 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); in b43_nphy_restore_rssi_cal()
4771 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); in b43_nphy_restore_rssi_cal()
4773 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); in b43_nphy_restore_rssi_cal()
4774 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); in b43_nphy_restore_rssi_cal()
4775 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); in b43_nphy_restore_rssi_cal()
4776 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); in b43_nphy_restore_rssi_cal()
4779 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup_rev19() argument
4784 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup_rev7() argument
4786 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_radio_setup_rev7()
4787 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_radio_setup_rev7()
4796 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); in b43_nphy_tx_cal_radio_setup_rev7()
4797 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); in b43_nphy_tx_cal_radio_setup_rev7()
4798 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); in b43_nphy_tx_cal_radio_setup_rev7()
4799 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); in b43_nphy_tx_cal_radio_setup_rev7()
4801 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); in b43_nphy_tx_cal_radio_setup_rev7()
4803 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); in b43_nphy_tx_cal_radio_setup_rev7()
4804 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); in b43_nphy_tx_cal_radio_setup_rev7()
4805 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); in b43_nphy_tx_cal_radio_setup_rev7()
4807 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_tx_cal_radio_setup_rev7()
4808 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); in b43_nphy_tx_cal_radio_setup_rev7()
4809 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4810 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4811 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4812 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4814 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); in b43_nphy_tx_cal_radio_setup_rev7()
4816 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); in b43_nphy_tx_cal_radio_setup_rev7()
4818 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); in b43_nphy_tx_cal_radio_setup_rev7()
4820 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4821 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4822 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4823 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4826 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4828 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4830 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); in b43_nphy_tx_cal_radio_setup_rev7()
4832 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4838 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup() argument
4840 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_radio_setup()
4841 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_radio_setup()
4847 b43_nphy_tx_cal_radio_setup_rev19(dev); in b43_nphy_tx_cal_radio_setup()
4849 b43_nphy_tx_cal_radio_setup_rev7(dev); in b43_nphy_tx_cal_radio_setup()
4855 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); in b43_nphy_tx_cal_radio_setup()
4856 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL); in b43_nphy_tx_cal_radio_setup()
4857 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS); in b43_nphy_tx_cal_radio_setup()
4858 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS); in b43_nphy_tx_cal_radio_setup()
4859 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS); in b43_nphy_tx_cal_radio_setup()
4860 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV); in b43_nphy_tx_cal_radio_setup()
4861 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1); in b43_nphy_tx_cal_radio_setup()
4862 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2); in b43_nphy_tx_cal_radio_setup()
4863 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL); in b43_nphy_tx_cal_radio_setup()
4864 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC); in b43_nphy_tx_cal_radio_setup()
4865 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1); in b43_nphy_tx_cal_radio_setup()
4867 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { in b43_nphy_tx_cal_radio_setup()
4868 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); in b43_nphy_tx_cal_radio_setup()
4869 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4870 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4871 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4872 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4874 b43_radio_write(dev, tmp | B2055_PADDRV, 4); in b43_nphy_tx_cal_radio_setup()
4875 b43_radio_write(dev, tmp | B2055_XOCTL1, 1); in b43_nphy_tx_cal_radio_setup()
4877 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4878 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); in b43_nphy_tx_cal_radio_setup()
4880 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4882 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); in b43_nphy_tx_cal_radio_setup()
4883 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4884 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4885 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4886 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4887 b43_radio_write(dev, tmp | B2055_XOCTL1, 0); in b43_nphy_tx_cal_radio_setup()
4889 b43_radio_write(dev, tmp | B2055_PADDRV, 6); in b43_nphy_tx_cal_radio_setup()
4890 b43_radio_write(dev, tmp | B2055_XOCTL2, in b43_nphy_tx_cal_radio_setup()
4891 (dev->phy.rev < 5) ? 0x11 : 0x01); in b43_nphy_tx_cal_radio_setup()
4893 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4894 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4897 b43_radio_write(dev, tmp | B2055_XOREGUL, 0); in b43_nphy_tx_cal_radio_setup()
4898 b43_radio_write(dev, tmp | B2055_XOMISC, 0); in b43_nphy_tx_cal_radio_setup()
4899 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); in b43_nphy_tx_cal_radio_setup()
4902 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4903 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4905 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2); in b43_nphy_tx_cal_radio_setup()
4906 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4908 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4909 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4911 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2); in b43_nphy_tx_cal_radio_setup()
4912 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4914 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX); in b43_nphy_tx_cal_radio_setup()
4915 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX); in b43_nphy_tx_cal_radio_setup()
4917 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & in b43_nphy_tx_cal_radio_setup()
4919 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4920 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4922 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4923 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4926 if (dev->phy.rev < 2) { in b43_nphy_tx_cal_radio_setup()
4927 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4928 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4930 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4931 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4937 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) in b43_nphy_update_tx_cal_ladder() argument
4939 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_update_tx_cal_ladder()
4951 b43_ntab_write(dev, B43_NTAB16(15, i), entry); in b43_nphy_update_tx_cal_ladder()
4955 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); in b43_nphy_update_tx_cal_ladder()
4959 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset, in b43_nphy_pa_set_tx_dig_filter() argument
4967 b43_phy_write(dev, offset, filter[i]); in b43_nphy_pa_set_tx_dig_filter()
4971 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) in b43_nphy_ext_pa_set_tx_dig_filters() argument
4973 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, in b43_nphy_ext_pa_set_tx_dig_filters()
4978 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) in b43_nphy_int_pa_set_tx_dig_filters() argument
4990 b43_nphy_pa_set_tx_dig_filter(dev, offset[i], in b43_nphy_int_pa_set_tx_dig_filters()
4994 if (dev->phy.rev == 16) in b43_nphy_int_pa_set_tx_dig_filters()
4995 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4998 if (dev->phy.rev == 17) { in b43_nphy_int_pa_set_tx_dig_filters()
4999 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
5000 b43_nphy_pa_set_tx_dig_filter(dev, 0x195, in b43_nphy_int_pa_set_tx_dig_filters()
5004 if (b43_is_40mhz(dev)) { in b43_nphy_int_pa_set_tx_dig_filters()
5005 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
5008 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) in b43_nphy_int_pa_set_tx_dig_filters()
5009 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
5011 if (dev->phy.channel == 14) in b43_nphy_int_pa_set_tx_dig_filters()
5012 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
5018 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) in b43_nphy_get_tx_gains() argument
5020 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_get_tx_gains()
5030 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_get_tx_gains()
5031 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); in b43_nphy_get_tx_gains()
5033 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_get_tx_gains()
5036 if (dev->phy.rev >= 7) { in b43_nphy_get_tx_gains()
5042 } else if (dev->phy.rev >= 3) { in b43_nphy_get_tx_gains()
5057 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5060 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5065 table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_get_tx_gains()
5069 if (dev->phy.rev >= 7) { in b43_nphy_get_tx_gains()
5075 } else if (dev->phy.rev >= 3) { in b43_nphy_get_tx_gains()
5093 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) in b43_nphy_tx_cal_phy_cleanup() argument
5095 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; in b43_nphy_tx_cal_phy_cleanup()
5097 if (dev->phy.rev >= 3) { in b43_nphy_tx_cal_phy_cleanup()
5098 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5099 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5100 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); in b43_nphy_tx_cal_phy_cleanup()
5101 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); in b43_nphy_tx_cal_phy_cleanup()
5102 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); in b43_nphy_tx_cal_phy_cleanup()
5103 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); in b43_nphy_tx_cal_phy_cleanup()
5104 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); in b43_nphy_tx_cal_phy_cleanup()
5105 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); in b43_nphy_tx_cal_phy_cleanup()
5106 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); in b43_nphy_tx_cal_phy_cleanup()
5107 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); in b43_nphy_tx_cal_phy_cleanup()
5108 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); in b43_nphy_tx_cal_phy_cleanup()
5109 b43_nphy_reset_cca(dev); in b43_nphy_tx_cal_phy_cleanup()
5111 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5112 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5113 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); in b43_nphy_tx_cal_phy_cleanup()
5114 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); in b43_nphy_tx_cal_phy_cleanup()
5115 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); in b43_nphy_tx_cal_phy_cleanup()
5116 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); in b43_nphy_tx_cal_phy_cleanup()
5117 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); in b43_nphy_tx_cal_phy_cleanup()
5122 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) in b43_nphy_tx_cal_phy_setup() argument
5124 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_phy_setup()
5125 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_phy_setup()
5126 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; in b43_nphy_tx_cal_phy_setup()
5129 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_tx_cal_phy_setup()
5130 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_tx_cal_phy_setup()
5131 if (dev->phy.rev >= 3) { in b43_nphy_tx_cal_phy_setup()
5132 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5133 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5135 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); in b43_nphy_tx_cal_phy_setup()
5137 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5139 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_tx_cal_phy_setup()
5141 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5143 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_nphy_tx_cal_phy_setup()
5144 b43_phy_mask(dev, B43_NPHY_BBCFG, in b43_nphy_tx_cal_phy_setup()
5147 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); in b43_nphy_tx_cal_phy_setup()
5149 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); in b43_nphy_tx_cal_phy_setup()
5151 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); in b43_nphy_tx_cal_phy_setup()
5153 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); in b43_nphy_tx_cal_phy_setup()
5154 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_tx_cal_phy_setup()
5155 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_tx_cal_phy_setup()
5158 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, in b43_nphy_tx_cal_phy_setup()
5161 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, in b43_nphy_tx_cal_phy_setup()
5163 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); in b43_nphy_tx_cal_phy_setup()
5164 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); in b43_nphy_tx_cal_phy_setup()
5166 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); in b43_nphy_tx_cal_phy_setup()
5167 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); in b43_nphy_tx_cal_phy_setup()
5168 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5169 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5171 tmp = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_tx_cal_phy_setup()
5173 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5176 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5181 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5184 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5187 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); in b43_nphy_tx_cal_phy_setup()
5188 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_tx_cal_phy_setup()
5189 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5190 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5192 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5193 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5198 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5199 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5200 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_tx_cal_phy_setup()
5202 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); in b43_nphy_tx_cal_phy_setup()
5203 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); in b43_nphy_tx_cal_phy_setup()
5206 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); in b43_nphy_tx_cal_phy_setup()
5207 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); in b43_nphy_tx_cal_phy_setup()
5210 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); in b43_nphy_tx_cal_phy_setup()
5211 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_tx_cal_phy_setup()
5212 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_tx_cal_phy_setup()
5213 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) in b43_nphy_tx_cal_phy_setup()
5217 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); in b43_nphy_tx_cal_phy_setup()
5218 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); in b43_nphy_tx_cal_phy_setup()
5223 static void b43_nphy_save_cal(struct b43_wldev *dev) in b43_nphy_save_cal() argument
5225 struct b43_phy *phy = &dev->phy; in b43_nphy_save_cal()
5226 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_save_cal()
5234 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_save_cal()
5236 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_save_cal()
5248 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); in b43_nphy_save_cal()
5253 txcal_radio_regs[0] = b43_radio_read(dev, in b43_nphy_save_cal()
5255 txcal_radio_regs[1] = b43_radio_read(dev, in b43_nphy_save_cal()
5257 txcal_radio_regs[4] = b43_radio_read(dev, in b43_nphy_save_cal()
5259 txcal_radio_regs[5] = b43_radio_read(dev, in b43_nphy_save_cal()
5261 txcal_radio_regs[2] = b43_radio_read(dev, in b43_nphy_save_cal()
5263 txcal_radio_regs[3] = b43_radio_read(dev, in b43_nphy_save_cal()
5265 txcal_radio_regs[6] = b43_radio_read(dev, in b43_nphy_save_cal()
5267 txcal_radio_regs[7] = b43_radio_read(dev, in b43_nphy_save_cal()
5270 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); in b43_nphy_save_cal()
5271 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); in b43_nphy_save_cal()
5272 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); in b43_nphy_save_cal()
5273 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); in b43_nphy_save_cal()
5274 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); in b43_nphy_save_cal()
5275 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); in b43_nphy_save_cal()
5276 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); in b43_nphy_save_cal()
5277 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); in b43_nphy_save_cal()
5279 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); in b43_nphy_save_cal()
5280 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); in b43_nphy_save_cal()
5281 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); in b43_nphy_save_cal()
5282 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); in b43_nphy_save_cal()
5284 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq; in b43_nphy_save_cal()
5286 cfg80211_get_chandef_type(dev->phy.chandef); in b43_nphy_save_cal()
5287 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); in b43_nphy_save_cal()
5290 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_save_cal()
5294 static void b43_nphy_restore_cal(struct b43_wldev *dev) in b43_nphy_restore_cal() argument
5296 struct b43_phy *phy = &dev->phy; in b43_nphy_restore_cal()
5297 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_restore_cal()
5307 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_restore_cal()
5319 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); in b43_nphy_restore_cal()
5322 if (dev->phy.rev >= 3) in b43_nphy_restore_cal()
5328 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); in b43_nphy_restore_cal()
5329 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); in b43_nphy_restore_cal()
5330 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); in b43_nphy_restore_cal()
5332 if (dev->phy.rev < 2) in b43_nphy_restore_cal()
5333 b43_nphy_tx_iq_workaround(dev); in b43_nphy_restore_cal()
5335 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_restore_cal()
5347 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, in b43_nphy_restore_cal()
5349 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, in b43_nphy_restore_cal()
5351 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, in b43_nphy_restore_cal()
5353 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, in b43_nphy_restore_cal()
5355 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, in b43_nphy_restore_cal()
5357 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, in b43_nphy_restore_cal()
5359 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, in b43_nphy_restore_cal()
5361 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, in b43_nphy_restore_cal()
5364 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5365 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5366 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5367 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5368 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); in b43_nphy_restore_cal()
5369 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); in b43_nphy_restore_cal()
5370 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); in b43_nphy_restore_cal()
5371 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); in b43_nphy_restore_cal()
5373 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5374 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5375 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5376 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5378 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); in b43_nphy_restore_cal()
5382 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, in b43_nphy_cal_tx_iq_lo() argument
5386 struct b43_phy *phy = &dev->phy; in b43_nphy_cal_tx_iq_lo()
5387 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_cal_tx_iq_lo()
5404 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_cal_tx_iq_lo()
5406 if (dev->phy.rev >= 4) { in b43_nphy_cal_tx_iq_lo()
5411 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5414 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); in b43_nphy_cal_tx_iq_lo()
5418 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); in b43_nphy_cal_tx_iq_lo()
5420 b43_nphy_tx_cal_radio_setup(dev); in b43_nphy_cal_tx_iq_lo()
5421 b43_nphy_tx_cal_phy_setup(dev); in b43_nphy_cal_tx_iq_lo()
5423 phy6or5x = dev->phy.rev >= 6 || in b43_nphy_cal_tx_iq_lo()
5424 (dev->phy.rev == 5 && nphy->ipa2g_on && in b43_nphy_cal_tx_iq_lo()
5425 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); in b43_nphy_cal_tx_iq_lo()
5427 if (b43_is_40mhz(dev)) { in b43_nphy_cal_tx_iq_lo()
5428 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5430 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, in b43_nphy_cal_tx_iq_lo()
5433 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5435 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, in b43_nphy_cal_tx_iq_lo()
5443 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); in b43_nphy_cal_tx_iq_lo()
5445 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); in b43_nphy_cal_tx_iq_lo()
5448 if (!b43_is_40mhz(dev)) in b43_nphy_cal_tx_iq_lo()
5454 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8, in b43_nphy_cal_tx_iq_lo()
5457 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false); in b43_nphy_cal_tx_iq_lo()
5463 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5469 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5473 if (dev->phy.rev >= 3) { in b43_nphy_cal_tx_iq_lo()
5483 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); in b43_nphy_cal_tx_iq_lo()
5486 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5491 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5508 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5513 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5523 b43_nphy_update_tx_cal_ladder(dev, core); in b43_nphy_cal_tx_iq_lo()
5528 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); in b43_nphy_cal_tx_iq_lo()
5531 buffer[0] = b43_ntab_read(dev, in b43_nphy_cal_tx_iq_lo()
5535 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), in b43_nphy_cal_tx_iq_lo()
5539 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); in b43_nphy_cal_tx_iq_lo()
5541 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); in b43_nphy_cal_tx_iq_lo()
5547 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, in b43_nphy_cal_tx_iq_lo()
5559 last = (dev->phy.rev < 3) ? 6 : 7; in b43_nphy_cal_tx_iq_lo()
5562 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); in b43_nphy_cal_tx_iq_lo()
5563 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); in b43_nphy_cal_tx_iq_lo()
5564 if (dev->phy.rev < 3) { in b43_nphy_cal_tx_iq_lo()
5570 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, in b43_nphy_cal_tx_iq_lo()
5572 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, in b43_nphy_cal_tx_iq_lo()
5574 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, in b43_nphy_cal_tx_iq_lo()
5576 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, in b43_nphy_cal_tx_iq_lo()
5579 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5581 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5590 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5592 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5596 b43_nphy_stop_playback(dev); in b43_nphy_cal_tx_iq_lo()
5597 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); in b43_nphy_cal_tx_iq_lo()
5600 b43_nphy_tx_cal_phy_cleanup(dev); in b43_nphy_cal_tx_iq_lo()
5601 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5603 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) in b43_nphy_cal_tx_iq_lo()
5604 b43_nphy_tx_iq_workaround(dev); in b43_nphy_cal_tx_iq_lo()
5606 if (dev->phy.rev >= 4) in b43_nphy_cal_tx_iq_lo()
5609 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_cal_tx_iq_lo()
5615 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) in b43_nphy_reapply_tx_cal_coeffs() argument
5617 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_reapply_tx_cal_coeffs()
5623 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq || in b43_nphy_reapply_tx_cal_coeffs()
5624 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef)) in b43_nphy_reapply_tx_cal_coeffs()
5627 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); in b43_nphy_reapply_tx_cal_coeffs()
5636 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, in b43_nphy_reapply_tx_cal_coeffs()
5640 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, in b43_nphy_reapply_tx_cal_coeffs()
5642 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, in b43_nphy_reapply_tx_cal_coeffs()
5644 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, in b43_nphy_reapply_tx_cal_coeffs()
5650 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_rev2_cal_rx_iq() argument
5653 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_rev2_cal_rx_iq()
5676 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_rev2_cal_rx_iq()
5678 if (dev->phy.rev < 2) in b43_nphy_rev2_cal_rx_iq()
5679 b43_nphy_reapply_tx_cal_coeffs(dev); in b43_nphy_rev2_cal_rx_iq()
5680 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5682 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); in b43_nphy_rev2_cal_rx_iq()
5685 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); in b43_nphy_rev2_cal_rx_iq()
5698 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); in b43_nphy_rev2_cal_rx_iq()
5699 tmp[2] = b43_phy_read(dev, afectl_core); in b43_nphy_rev2_cal_rx_iq()
5700 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_rev2_cal_rx_iq()
5701 tmp[4] = b43_phy_read(dev, rfctl[0]); in b43_nphy_rev2_cal_rx_iq()
5702 tmp[5] = b43_phy_read(dev, rfctl[1]); in b43_nphy_rev2_cal_rx_iq()
5704 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, in b43_nphy_rev2_cal_rx_iq()
5707 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, in b43_nphy_rev2_cal_rx_iq()
5709 b43_phy_set(dev, afectl_core, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5710 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5712 band = b43_current_band(dev->wl); in b43_nphy_rev2_cal_rx_iq()
5716 b43_phy_write(dev, rfctl[0], 0x140); in b43_nphy_rev2_cal_rx_iq()
5718 b43_phy_write(dev, rfctl[0], 0x110); in b43_nphy_rev2_cal_rx_iq()
5721 b43_phy_write(dev, rfctl[0], 0x180); in b43_nphy_rev2_cal_rx_iq()
5723 b43_phy_write(dev, rfctl[0], 0x120); in b43_nphy_rev2_cal_rx_iq()
5727 b43_phy_write(dev, rfctl[1], 0x148); in b43_nphy_rev2_cal_rx_iq()
5729 b43_phy_write(dev, rfctl[1], 0x114); in b43_nphy_rev2_cal_rx_iq()
5732 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5734 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5772 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, in b43_nphy_rev2_cal_rx_iq()
5774 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev2_cal_rx_iq()
5775 b43_nphy_stop_playback(dev); in b43_nphy_rev2_cal_rx_iq()
5778 ret = b43_nphy_tx_tone(dev, 4000, in b43_nphy_rev2_cal_rx_iq()
5783 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, in b43_nphy_rev2_cal_rx_iq()
5789 b43_nphy_rx_iq_est(dev, &est, 1024, 32, in b43_nphy_rev2_cal_rx_iq()
5800 b43_nphy_calc_rx_iq_comp(dev, 1 << i); in b43_nphy_rev2_cal_rx_iq()
5802 b43_nphy_stop_playback(dev); in b43_nphy_rev2_cal_rx_iq()
5809 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5810 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5811 b43_phy_write(dev, rfctl[1], tmp[5]); in b43_nphy_rev2_cal_rx_iq()
5812 b43_phy_write(dev, rfctl[0], tmp[4]); in b43_nphy_rev2_cal_rx_iq()
5813 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); in b43_nphy_rev2_cal_rx_iq()
5814 b43_phy_write(dev, afectl_core, tmp[2]); in b43_nphy_rev2_cal_rx_iq()
5815 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); in b43_nphy_rev2_cal_rx_iq()
5821 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); in b43_nphy_rev2_cal_rx_iq()
5822 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev2_cal_rx_iq()
5823 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5825 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_rev2_cal_rx_iq()
5830 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_rev3_cal_rx_iq() argument
5837 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_cal_rx_iq() argument
5840 if (dev->phy.rev >= 7) in b43_nphy_cal_rx_iq()
5843 if (dev->phy.rev >= 3) in b43_nphy_cal_rx_iq()
5844 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); in b43_nphy_cal_rx_iq()
5846 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); in b43_nphy_cal_rx_iq()
5850 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) in b43_nphy_set_rx_core_state() argument
5852 struct b43_phy *phy = &dev->phy; in b43_nphy_set_rx_core_state()
5861 b43_mac_suspend(dev); in b43_nphy_set_rx_core_state()
5864 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_set_rx_core_state()
5866 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, in b43_nphy_set_rx_core_state()
5870 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); in b43_nphy_set_rx_core_state()
5871 if (dev->phy.rev >= 3) { in b43_nphy_set_rx_core_state()
5875 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); in b43_nphy_set_rx_core_state()
5876 if (dev->phy.rev >= 3) { in b43_nphy_set_rx_core_state()
5881 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_set_rx_core_state()
5884 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_set_rx_core_state()
5886 b43_mac_enable(dev); in b43_nphy_set_rx_core_state()
5889 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, in b43_nphy_op_recalc_txpower() argument
5892 struct b43_phy *phy = &dev->phy; in b43_nphy_op_recalc_txpower()
5893 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_op_recalc_txpower()
5894 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; in b43_nphy_op_recalc_txpower()
5904 b43_ppr_clear(dev, ppr); in b43_nphy_op_recalc_txpower()
5907 b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G); in b43_nphy_op_recalc_txpower()
5913 b43_ppr_apply_max(dev, ppr, max); in b43_nphy_op_recalc_txpower()
5914 if (b43_debug(dev, B43_DBG_XMITPOWER)) in b43_nphy_op_recalc_txpower()
5915 b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n", in b43_nphy_op_recalc_txpower()
5916 Q52_ARG(b43_ppr_get_max(dev, ppr))); in b43_nphy_op_recalc_txpower()
5922 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_op_recalc_txpower()
5926 b43_ppr_add(dev, ppr, -hw_gain); in b43_nphy_op_recalc_txpower()
5930 b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8)); in b43_nphy_op_recalc_txpower()
5934 b43_mac_suspend(dev); in b43_nphy_op_recalc_txpower()
5935 b43_nphy_tx_power_ctl_setup(dev); in b43_nphy_op_recalc_txpower()
5936 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_op_recalc_txpower()
5937 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); in b43_nphy_op_recalc_txpower()
5938 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_op_recalc_txpower()
5941 b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl); in b43_nphy_op_recalc_txpower()
5942 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_op_recalc_txpower()
5943 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); in b43_nphy_op_recalc_txpower()
5944 b43_mac_enable(dev); in b43_nphy_op_recalc_txpower()
5957 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) in b43_nphy_update_mimo_config() argument
5959 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); in b43_nphy_update_mimo_config()
5967 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); in b43_nphy_update_mimo_config()
5971 static void b43_nphy_bphy_init(struct b43_wldev *dev) in b43_nphy_bphy_init() argument
5978 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); in b43_nphy_bphy_init()
5983 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); in b43_nphy_bphy_init()
5986 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); in b43_nphy_bphy_init()
5990 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) in b43_nphy_superswitch_init() argument
5992 if (dev->phy.rev >= 7) in b43_nphy_superswitch_init()
5995 if (dev->phy.rev >= 3) { in b43_nphy_superswitch_init()
5999 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); in b43_nphy_superswitch_init()
6000 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); in b43_nphy_superswitch_init()
6001 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); in b43_nphy_superswitch_init()
6002 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); in b43_nphy_superswitch_init()
6005 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); in b43_nphy_superswitch_init()
6006 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); in b43_nphy_superswitch_init()
6008 switch (dev->dev->bus_type) { in b43_nphy_superswitch_init()
6011 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, in b43_nphy_superswitch_init()
6017 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco, in b43_nphy_superswitch_init()
6023 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); in b43_nphy_superswitch_init()
6024 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); in b43_nphy_superswitch_init()
6025 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), in b43_nphy_superswitch_init()
6029 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_superswitch_init()
6030 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_superswitch_init()
6031 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_superswitch_init()
6032 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_superswitch_init()
6038 static int b43_phy_initn(struct b43_wldev *dev) in b43_phy_initn() argument
6040 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_phy_initn()
6041 struct b43_phy *phy = &dev->phy; in b43_phy_initn()
6052 if ((dev->phy.rev >= 3) && in b43_phy_initn()
6054 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { in b43_phy_initn()
6055 switch (dev->dev->bus_type) { in b43_phy_initn()
6058 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc, in b43_phy_initn()
6064 chipco_set32(&dev->dev->sdev->bus->chipco, in b43_phy_initn()
6070 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || in b43_phy_initn()
6075 b43_nphy_tables_init(dev); in b43_phy_initn()
6080 if (dev->phy.rev >= 3) { in b43_phy_initn()
6081 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); in b43_phy_initn()
6082 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6084 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); in b43_phy_initn()
6085 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); in b43_phy_initn()
6086 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); in b43_phy_initn()
6087 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); in b43_phy_initn()
6093 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); in b43_phy_initn()
6094 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); in b43_phy_initn()
6096 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6098 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); in b43_phy_initn()
6099 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); in b43_phy_initn()
6100 if (dev->phy.rev < 6) { in b43_phy_initn()
6101 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); in b43_phy_initn()
6102 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); in b43_phy_initn()
6104 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, in b43_phy_initn()
6107 if (dev->phy.rev >= 3) in b43_phy_initn()
6108 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); in b43_phy_initn()
6109 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); in b43_phy_initn()
6111 if (dev->phy.rev <= 2) { in b43_phy_initn()
6112 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; in b43_phy_initn()
6113 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_phy_initn()
6117 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); in b43_phy_initn()
6118 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); in b43_phy_initn()
6121 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && in b43_phy_initn()
6122 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93)) in b43_phy_initn()
6123 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); in b43_phy_initn()
6125 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); in b43_phy_initn()
6126 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); in b43_phy_initn()
6127 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); in b43_phy_initn()
6128 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); in b43_phy_initn()
6131 b43_nphy_update_mimo_config(dev, nphy->preamble_override); in b43_phy_initn()
6133 b43_nphy_update_txrx_chain(dev); in b43_phy_initn()
6136 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); in b43_phy_initn()
6137 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); in b43_phy_initn()
6140 tmp2 = b43_current_band(dev->wl); in b43_phy_initn()
6141 if (b43_nphy_ipa(dev)) { in b43_phy_initn()
6142 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); in b43_phy_initn()
6143 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, in b43_phy_initn()
6145 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); in b43_phy_initn()
6146 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, in b43_phy_initn()
6148 b43_nphy_int_pa_set_tx_dig_filters(dev); in b43_phy_initn()
6150 b43_nphy_ext_pa_set_tx_dig_filters(dev); in b43_phy_initn()
6153 b43_nphy_workarounds(dev); in b43_phy_initn()
6156 b43_phy_force_clock(dev, 1); in b43_phy_initn()
6157 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_phy_initn()
6158 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); in b43_phy_initn()
6159 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); in b43_phy_initn()
6160 b43_phy_force_clock(dev, 0); in b43_phy_initn()
6162 b43_mac_phy_clock_set(dev, true); in b43_phy_initn()
6165 b43_nphy_pa_override(dev, false); in b43_phy_initn()
6166 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); in b43_phy_initn()
6167 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_phy_initn()
6168 b43_nphy_pa_override(dev, true); in b43_phy_initn()
6171 b43_nphy_classifier(dev, 0, 0); in b43_phy_initn()
6172 b43_nphy_read_clip_detection(dev, clip); in b43_phy_initn()
6173 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_phy_initn()
6174 b43_nphy_bphy_init(dev); in b43_phy_initn()
6177 b43_nphy_tx_power_ctrl(dev, false); in b43_phy_initn()
6178 b43_nphy_tx_power_fix(dev); in b43_phy_initn()
6179 b43_nphy_tx_power_ctl_idle_tssi(dev); in b43_phy_initn()
6180 b43_nphy_tx_power_ctl_setup(dev); in b43_phy_initn()
6181 b43_nphy_tx_gain_table_upload(dev); in b43_phy_initn()
6184 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); in b43_phy_initn()
6190 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_phy_initn()
6196 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6198 b43_nphy_restore_rssi_cal(dev); in b43_phy_initn()
6200 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6204 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_phy_initn()
6213 target = b43_nphy_get_tx_gains(dev); in b43_phy_initn()
6216 b43_nphy_superswitch_init(dev, true); in b43_phy_initn()
6218 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6225 target = b43_nphy_get_tx_gains(dev); in b43_phy_initn()
6227 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) in b43_phy_initn()
6228 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) in b43_phy_initn()
6229 b43_nphy_save_cal(dev); in b43_phy_initn()
6233 b43_nphy_restore_cal(dev); in b43_phy_initn()
6237 b43_nphy_tx_pwr_ctrl_coef_setup(dev); in b43_phy_initn()
6238 b43_nphy_tx_power_ctrl(dev, tx_pwr_state); in b43_phy_initn()
6239 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); in b43_phy_initn()
6240 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); in b43_phy_initn()
6242 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); in b43_phy_initn()
6243 b43_nphy_tx_lpf_bw(dev); in b43_phy_initn()
6245 b43_nphy_spur_workaround(dev); in b43_phy_initn()
6254 static void b43_chantab_phy_upload(struct b43_wldev *dev, in b43_chantab_phy_upload() argument
6257 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); in b43_chantab_phy_upload()
6258 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); in b43_chantab_phy_upload()
6259 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); in b43_chantab_phy_upload()
6260 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); in b43_chantab_phy_upload()
6261 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); in b43_chantab_phy_upload()
6262 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); in b43_chantab_phy_upload()
6266 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) in b43_nphy_pmu_spur_avoid() argument
6268 switch (dev->dev->bus_type) { in b43_nphy_pmu_spur_avoid()
6271 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc, in b43_nphy_pmu_spur_avoid()
6277 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, in b43_nphy_pmu_spur_avoid()
6285 static void b43_nphy_channel_setup(struct b43_wldev *dev, in b43_nphy_channel_setup() argument
6289 struct b43_phy *phy = &dev->phy; in b43_nphy_channel_setup()
6290 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_channel_setup()
6296 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6298 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); in b43_nphy_channel_setup()
6299 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); in b43_nphy_channel_setup()
6301 b43_phy_set(dev, B43_PHY_B_BBCFG, in b43_nphy_channel_setup()
6303 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); in b43_nphy_channel_setup()
6304 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6306 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6307 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); in b43_nphy_channel_setup()
6308 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); in b43_nphy_channel_setup()
6310 b43_phy_mask(dev, B43_PHY_B_BBCFG, in b43_nphy_channel_setup()
6312 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); in b43_nphy_channel_setup()
6315 b43_chantab_phy_upload(dev, e); in b43_nphy_channel_setup()
6318 b43_nphy_classifier(dev, 2, 0); in b43_nphy_channel_setup()
6319 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); in b43_nphy_channel_setup()
6321 b43_nphy_classifier(dev, 2, 2); in b43_nphy_channel_setup()
6323 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); in b43_nphy_channel_setup()
6327 b43_nphy_tx_power_fix(dev); in b43_nphy_channel_setup()
6329 if (dev->phy.rev < 3) in b43_nphy_channel_setup()
6330 b43_nphy_adjust_lna_gain_table(dev); in b43_nphy_channel_setup()
6332 b43_nphy_tx_lpf_bw(dev); in b43_nphy_channel_setup()
6334 if (dev->phy.rev >= 3 && in b43_nphy_channel_setup()
6335 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) { in b43_nphy_channel_setup()
6338 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) { in b43_nphy_channel_setup()
6349 if (!b43_is_40mhz(dev)) { /* 20MHz */ in b43_nphy_channel_setup()
6357 if (!b43_is_40mhz(dev)) { /* 20MHz */ in b43_nphy_channel_setup()
6363 spuravoid = dev->dev->chip_id == 0x4716; in b43_nphy_channel_setup()
6367 b43_nphy_pmu_spur_avoid(dev, spuravoid); in b43_nphy_channel_setup()
6369 b43_mac_switch_freq(dev, spuravoid); in b43_nphy_channel_setup()
6371 if (dev->phy.rev == 3 || dev->phy.rev == 4) in b43_nphy_channel_setup()
6372 b43_wireless_core_phy_pll_reset(dev); in b43_nphy_channel_setup()
6375 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX); in b43_nphy_channel_setup()
6377 b43_phy_mask(dev, B43_NPHY_BBCFG, in b43_nphy_channel_setup()
6380 b43_nphy_reset_cca(dev); in b43_nphy_channel_setup()
6385 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); in b43_nphy_channel_setup()
6388 b43_nphy_spur_workaround(dev); in b43_nphy_channel_setup()
6392 static int b43_nphy_set_channel(struct b43_wldev *dev, in b43_nphy_set_channel() argument
6396 struct b43_phy *phy = &dev->phy; in b43_nphy_set_channel()
6409 r2057_get_chantabent_rev7(dev, channel->center_freq, in b43_nphy_set_channel()
6414 tabent_r3 = b43_nphy_get_chantabent_rev3(dev, in b43_nphy_set_channel()
6419 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, in b43_nphy_set_channel()
6436 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20); in b43_nphy_set_channel()
6438 b43_phy_set(dev, 0x310, 0x8000); in b43_nphy_set_channel()
6440 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20); in b43_nphy_set_channel()
6442 b43_phy_mask(dev, 0x310, (u16)~0x8000); in b43_nphy_set_channel()
6453 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp); in b43_nphy_set_channel()
6454 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp); in b43_nphy_set_channel()
6457 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g); in b43_nphy_set_channel()
6458 b43_nphy_channel_setup(dev, phy_regs, channel); in b43_nphy_set_channel()
6461 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); in b43_nphy_set_channel()
6462 b43_radio_2056_setup(dev, tabent_r3); in b43_nphy_set_channel()
6463 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); in b43_nphy_set_channel()
6466 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); in b43_nphy_set_channel()
6467 b43_radio_2055_setup(dev, tabent_r2); in b43_nphy_set_channel()
6468 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); in b43_nphy_set_channel()
6478 static int b43_nphy_op_allocate(struct b43_wldev *dev) in b43_nphy_op_allocate() argument
6486 dev->phy.n = nphy; in b43_nphy_op_allocate()
6491 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) in b43_nphy_op_prepare_structs() argument
6493 struct b43_phy *phy = &dev->phy; in b43_nphy_op_prepare_structs()
6495 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_op_prepare_structs()
6514 if (dev->phy.rev >= 3 || in b43_nphy_op_prepare_structs()
6515 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && in b43_nphy_op_prepare_structs()
6516 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) { in b43_nphy_op_prepare_structs()
6520 if (dev->phy.rev >= 2 && in b43_nphy_op_prepare_structs()
6524 if (dev->dev->bus_type == B43_BUS_SSB && in b43_nphy_op_prepare_structs()
6525 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { in b43_nphy_op_prepare_structs()
6527 dev->dev->sdev->bus->host_pci; in b43_nphy_op_prepare_structs()
6538 if (dev->phy.rev >= 3) { in b43_nphy_op_prepare_structs()
6544 static void b43_nphy_op_free(struct b43_wldev *dev) in b43_nphy_op_free() argument
6546 struct b43_phy *phy = &dev->phy; in b43_nphy_op_free()
6553 static int b43_nphy_op_init(struct b43_wldev *dev) in b43_nphy_op_init() argument
6555 return b43_phy_initn(dev); in b43_nphy_op_init()
6558 static inline void check_phyreg(struct b43_wldev *dev, u16 offset) in check_phyreg() argument
6563 b43err(dev->wl, "Invalid OFDM PHY access at " in check_phyreg()
6569 b43err(dev->wl, "Invalid EXT-G PHY access at " in check_phyreg()
6576 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, in b43_nphy_op_maskset() argument
6579 check_phyreg(dev, reg); in b43_nphy_op_maskset()
6580 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_nphy_op_maskset()
6581 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); in b43_nphy_op_maskset()
6582 dev->phy.writes_counter = 1; in b43_nphy_op_maskset()
6585 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_nphy_op_radio_read() argument
6588 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); in b43_nphy_op_radio_read()
6590 if (dev->phy.rev >= 7) in b43_nphy_op_radio_read()
6595 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_nphy_op_radio_read()
6596 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_nphy_op_radio_read()
6599 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_nphy_op_radio_write() argument
6602 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); in b43_nphy_op_radio_write()
6604 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_nphy_op_radio_write()
6605 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_nphy_op_radio_write()
6609 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, in b43_nphy_op_software_rfkill() argument
6612 struct b43_phy *phy = &dev->phy; in b43_nphy_op_software_rfkill()
6614 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) in b43_nphy_op_software_rfkill()
6615 b43err(dev->wl, "MAC not suspended\n"); in b43_nphy_op_software_rfkill()
6621 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_op_software_rfkill()
6626 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_op_software_rfkill()
6629 b43_radio_mask(dev, 0x09, ~0x2); in b43_nphy_op_software_rfkill()
6631 b43_radio_write(dev, 0x204D, 0); in b43_nphy_op_software_rfkill()
6632 b43_radio_write(dev, 0x2053, 0); in b43_nphy_op_software_rfkill()
6633 b43_radio_write(dev, 0x2058, 0); in b43_nphy_op_software_rfkill()
6634 b43_radio_write(dev, 0x205E, 0); in b43_nphy_op_software_rfkill()
6635 b43_radio_mask(dev, 0x2062, ~0xF0); in b43_nphy_op_software_rfkill()
6636 b43_radio_write(dev, 0x2064, 0); in b43_nphy_op_software_rfkill()
6638 b43_radio_write(dev, 0x304D, 0); in b43_nphy_op_software_rfkill()
6639 b43_radio_write(dev, 0x3053, 0); in b43_nphy_op_software_rfkill()
6640 b43_radio_write(dev, 0x3058, 0); in b43_nphy_op_software_rfkill()
6641 b43_radio_write(dev, 0x305E, 0); in b43_nphy_op_software_rfkill()
6642 b43_radio_mask(dev, 0x3062, ~0xF0); in b43_nphy_op_software_rfkill()
6643 b43_radio_write(dev, 0x3064, 0); in b43_nphy_op_software_rfkill()
6649 if (!dev->phy.radio_on) in b43_nphy_op_software_rfkill()
6650 b43_radio_2057_init(dev); in b43_nphy_op_software_rfkill()
6651 b43_switch_channel(dev, dev->phy.channel); in b43_nphy_op_software_rfkill()
6653 if (!dev->phy.radio_on) in b43_nphy_op_software_rfkill()
6654 b43_radio_init2056(dev); in b43_nphy_op_software_rfkill()
6655 b43_switch_channel(dev, dev->phy.channel); in b43_nphy_op_software_rfkill()
6657 b43_radio_init2055(dev); in b43_nphy_op_software_rfkill()
6663 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) in b43_nphy_op_switch_analog() argument
6665 struct b43_phy *phy = &dev->phy; in b43_nphy_op_switch_analog()
6673 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); in b43_nphy_op_switch_analog()
6674 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); in b43_nphy_op_switch_analog()
6675 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); in b43_nphy_op_switch_analog()
6676 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6678 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); in b43_nphy_op_switch_analog()
6679 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); in b43_nphy_op_switch_analog()
6680 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6681 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); in b43_nphy_op_switch_analog()
6684 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6688 static int b43_nphy_op_switch_channel(struct b43_wldev *dev, in b43_nphy_op_switch_channel() argument
6691 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; in b43_nphy_op_switch_channel()
6693 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); in b43_nphy_op_switch_channel()
6695 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in b43_nphy_op_switch_channel()
6703 return b43_nphy_set_channel(dev, channel, channel_type); in b43_nphy_op_switch_channel()
6706 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) in b43_nphy_op_get_default_chan() argument
6708 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_nphy_op_get_default_chan()