217 	b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);  in lpphy_baseband_rev0_1_init()
218 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);  in lpphy_baseband_rev0_1_init()
219 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);  in lpphy_baseband_rev0_1_init()
220 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);  in lpphy_baseband_rev0_1_init()
224 	b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);  in lpphy_baseband_rev0_1_init()
257 	b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);  in lpphy_baseband_rev0_1_init()
324 		b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);  in lpphy_baseband_rev0_1_init()
325 		b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);  in lpphy_baseband_rev0_1_init()
346 		b43_phy_write(dev, B43_LPPHY_4C3, tmp2);  in lpphy_baseband_rev0_1_init()
350 		b43_phy_write(dev, B43_LPPHY_4C4, tmp2);  in lpphy_baseband_rev0_1_init()
354 		b43_phy_write(dev, B43_LPPHY_4C5, tmp2);  in lpphy_baseband_rev0_1_init()
383 		b43_phy_write(dev, addr[i], coefs[i]);  in lpphy_save_dig_flt_state()
405 		b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);  in lpphy_restore_dig_flt_state()
412 	b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);  in lpphy_baseband_rev2plus_init()
413 	b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);  in lpphy_baseband_rev2plus_init()
414 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);  in lpphy_baseband_rev2plus_init()
415 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);  in lpphy_baseband_rev2plus_init()
416 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);  in lpphy_baseband_rev2plus_init()
417 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);  in lpphy_baseband_rev2plus_init()
418 	b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);  in lpphy_baseband_rev2plus_init()
419 	b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);  in lpphy_baseband_rev2plus_init()
437 	b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);  in lpphy_baseband_rev2plus_init()
483 	b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);  in lpphy_baseband_rev2plus_init()
484 	b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);  in lpphy_baseband_rev2plus_init()
485 	b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,  in lpphy_baseband_rev2plus_init()
692 		b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);  in lpphy_radio_init()
693 		b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);  in lpphy_radio_init()
784 	b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);  in lpphy_disable_crs()
785 	b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);  in lpphy_disable_crs()
786 	b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);  in lpphy_disable_crs()
789 	b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);  in lpphy_disable_crs()
790 	b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);  in lpphy_disable_crs()
791 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);  in lpphy_disable_crs()
908 		b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,  in lpphy_set_tx_gains()
916 		b43_phy_write(dev, B43_PHY_OFDM(0xFC),  in lpphy_set_tx_gains()
936 	b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);  in lpphy_rev0_1_set_rx_gain()
952 	b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);  in lpphy_rev2plus_set_rx_gain()
1005 	b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);  in lpphy_rx_iq_est()
1260 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);  in lpphy_rev0_1_rc_calib()
1261 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);  in lpphy_rev0_1_rc_calib()
1262 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);  in lpphy_rev0_1_rc_calib()
1263 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);  in lpphy_rev0_1_rc_calib()
1264 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);  in lpphy_rev0_1_rc_calib()
1265 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);  in lpphy_rev0_1_rc_calib()
1266 	b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);  in lpphy_rev0_1_rc_calib()
1517 	b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);  in lpphy_tx_pctl_init_hw()