Lines Matching refs:dev
47 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev) in b43_lpphy_op_get_default_chan() argument
49 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in b43_lpphy_op_get_default_chan()
54 static int b43_lpphy_op_allocate(struct b43_wldev *dev) in b43_lpphy_op_allocate() argument
61 dev->phy.lp = lpphy; in b43_lpphy_op_allocate()
66 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev) in b43_lpphy_op_prepare_structs() argument
68 struct b43_phy *phy = &dev->phy; in b43_lpphy_op_prepare_structs()
77 static void b43_lpphy_op_free(struct b43_wldev *dev) in b43_lpphy_op_free() argument
79 struct b43_phy_lp *lpphy = dev->phy.lp; in b43_lpphy_op_free()
82 dev->phy.lp = NULL; in b43_lpphy_op_free()
86 static void lpphy_read_band_sprom(struct b43_wldev *dev) in lpphy_read_band_sprom() argument
88 struct ssb_sprom *sprom = dev->dev->bus_sprom; in lpphy_read_band_sprom()
89 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_read_band_sprom()
94 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_read_band_sprom()
169 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq) in lpphy_adjust_gain_table() argument
171 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_adjust_gain_table()
175 B43_WARN_ON(dev->phy.rev >= 2); in lpphy_adjust_gain_table()
177 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in lpphy_adjust_gain_table()
190 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp); in lpphy_adjust_gain_table()
191 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp); in lpphy_adjust_gain_table()
194 static void lpphy_table_init(struct b43_wldev *dev) in lpphy_table_init() argument
196 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev)); in lpphy_table_init()
198 if (dev->phy.rev < 2) in lpphy_table_init()
199 lpphy_rev0_1_table_init(dev); in lpphy_table_init()
201 lpphy_rev2plus_table_init(dev); in lpphy_table_init()
203 lpphy_init_tx_gain_table(dev); in lpphy_table_init()
205 if (dev->phy.rev < 2) in lpphy_table_init()
206 lpphy_adjust_gain_table(dev, freq); in lpphy_table_init()
209 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev) in lpphy_baseband_rev0_1_init() argument
211 struct ssb_bus *bus = dev->dev->sdev->bus; in lpphy_baseband_rev0_1_init()
212 struct ssb_sprom *sprom = dev->dev->bus_sprom; in lpphy_baseband_rev0_1_init()
213 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_baseband_rev0_1_init()
216 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF); in lpphy_baseband_rev0_1_init()
217 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0); in lpphy_baseband_rev0_1_init()
218 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0); in lpphy_baseband_rev0_1_init()
219 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0); in lpphy_baseband_rev0_1_init()
220 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0); in lpphy_baseband_rev0_1_init()
221 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004); in lpphy_baseband_rev0_1_init()
222 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078); in lpphy_baseband_rev0_1_init()
223 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800); in lpphy_baseband_rev0_1_init()
224 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016); in lpphy_baseband_rev0_1_init()
225 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004); in lpphy_baseband_rev0_1_init()
226 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400); in lpphy_baseband_rev0_1_init()
227 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400); in lpphy_baseband_rev0_1_init()
228 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100); in lpphy_baseband_rev0_1_init()
229 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006); in lpphy_baseband_rev0_1_init()
230 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE); in lpphy_baseband_rev0_1_init()
231 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005); in lpphy_baseband_rev0_1_init()
232 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180); in lpphy_baseband_rev0_1_init()
233 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00); in lpphy_baseband_rev0_1_init()
234 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005); in lpphy_baseband_rev0_1_init()
235 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A); in lpphy_baseband_rev0_1_init()
236 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3); in lpphy_baseband_rev0_1_init()
237 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00); in lpphy_baseband_rev0_1_init()
238 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, in lpphy_baseband_rev0_1_init()
241 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || in lpphy_baseband_rev0_1_init()
245 if (dev->phy.rev == 0) { in lpphy_baseband_rev0_1_init()
246 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT, in lpphy_baseband_rev0_1_init()
249 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60); in lpphy_baseband_rev0_1_init()
252 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT, in lpphy_baseband_rev0_1_init()
254 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100); in lpphy_baseband_rev0_1_init()
257 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp); in lpphy_baseband_rev0_1_init()
259 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA); in lpphy_baseband_rev0_1_init()
261 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA); in lpphy_baseband_rev0_1_init()
262 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24); in lpphy_baseband_rev0_1_init()
263 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL, in lpphy_baseband_rev0_1_init()
265 if (dev->phy.rev == 1 && in lpphy_baseband_rev0_1_init()
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900); in lpphy_baseband_rev0_1_init()
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00); in lpphy_baseband_rev0_1_init()
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400); in lpphy_baseband_rev0_1_init()
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00); in lpphy_baseband_rev0_1_init()
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900); in lpphy_baseband_rev0_1_init()
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00); in lpphy_baseband_rev0_1_init()
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900); in lpphy_baseband_rev0_1_init()
281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00); in lpphy_baseband_rev0_1_init()
283 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ || in lpphy_baseband_rev0_1_init()
284 (dev->dev->board_type == SSB_BOARD_BU4312) || in lpphy_baseband_rev0_1_init()
285 (dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) { in lpphy_baseband_rev0_1_init()
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001); in lpphy_baseband_rev0_1_init()
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400); in lpphy_baseband_rev0_1_init()
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001); in lpphy_baseband_rev0_1_init()
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500); in lpphy_baseband_rev0_1_init()
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002); in lpphy_baseband_rev0_1_init()
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800); in lpphy_baseband_rev0_1_init()
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002); in lpphy_baseband_rev0_1_init()
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00); in lpphy_baseband_rev0_1_init()
294 } else if (dev->phy.rev == 1 || in lpphy_baseband_rev0_1_init()
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004); in lpphy_baseband_rev0_1_init()
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800); in lpphy_baseband_rev0_1_init()
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004); in lpphy_baseband_rev0_1_init()
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00); in lpphy_baseband_rev0_1_init()
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002); in lpphy_baseband_rev0_1_init()
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100); in lpphy_baseband_rev0_1_init()
302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002); in lpphy_baseband_rev0_1_init()
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300); in lpphy_baseband_rev0_1_init()
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900); in lpphy_baseband_rev0_1_init()
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A); in lpphy_baseband_rev0_1_init()
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00); in lpphy_baseband_rev0_1_init()
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006); in lpphy_baseband_rev0_1_init()
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500); in lpphy_baseband_rev0_1_init()
311 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006); in lpphy_baseband_rev0_1_init()
312 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700); in lpphy_baseband_rev0_1_init()
314 if (dev->phy.rev == 1 && (sprom->boardflags_hi & B43_BFH_PAREF)) { in lpphy_baseband_rev0_1_init()
315 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1); in lpphy_baseband_rev0_1_init()
316 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2); in lpphy_baseband_rev0_1_init()
317 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3); in lpphy_baseband_rev0_1_init()
318 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4); in lpphy_baseband_rev0_1_init()
321 (dev->dev->chip_id == 0x5354) && in lpphy_baseband_rev0_1_init()
322 (dev->dev->chip_pkg == SSB_CHIPPACK_BCM4712S)) { in lpphy_baseband_rev0_1_init()
323 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006); in lpphy_baseband_rev0_1_init()
324 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005); in lpphy_baseband_rev0_1_init()
325 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF); in lpphy_baseband_rev0_1_init()
327 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W); in lpphy_baseband_rev0_1_init()
329 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_baseband_rev0_1_init()
330 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000); in lpphy_baseband_rev0_1_init()
331 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040); in lpphy_baseband_rev0_1_init()
332 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400); in lpphy_baseband_rev0_1_init()
333 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00); in lpphy_baseband_rev0_1_init()
334 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007); in lpphy_baseband_rev0_1_init()
335 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003); in lpphy_baseband_rev0_1_init()
336 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020); in lpphy_baseband_rev0_1_init()
337 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev0_1_init()
339 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF); in lpphy_baseband_rev0_1_init()
340 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF); in lpphy_baseband_rev0_1_init()
342 if (dev->phy.rev == 1) { in lpphy_baseband_rev0_1_init()
343 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH); in lpphy_baseband_rev0_1_init()
346 b43_phy_write(dev, B43_LPPHY_4C3, tmp2); in lpphy_baseband_rev0_1_init()
347 tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH); in lpphy_baseband_rev0_1_init()
350 b43_phy_write(dev, B43_LPPHY_4C4, tmp2); in lpphy_baseband_rev0_1_init()
351 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB); in lpphy_baseband_rev0_1_init()
354 b43_phy_write(dev, B43_LPPHY_4C5, tmp2); in lpphy_baseband_rev0_1_init()
358 static void lpphy_save_dig_flt_state(struct b43_wldev *dev) in lpphy_save_dig_flt_state() argument
378 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_save_dig_flt_state()
382 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]); in lpphy_save_dig_flt_state()
383 b43_phy_write(dev, addr[i], coefs[i]); in lpphy_save_dig_flt_state()
387 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev) in lpphy_restore_dig_flt_state() argument
401 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_restore_dig_flt_state()
405 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]); in lpphy_restore_dig_flt_state()
408 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev) in lpphy_baseband_rev2plus_init() argument
410 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_baseband_rev2plus_init()
412 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50); in lpphy_baseband_rev2plus_init()
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800); in lpphy_baseband_rev2plus_init()
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0); in lpphy_baseband_rev2plus_init()
415 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0); in lpphy_baseband_rev2plus_init()
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0); in lpphy_baseband_rev2plus_init()
417 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0); in lpphy_baseband_rev2plus_init()
418 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0); in lpphy_baseband_rev2plus_init()
419 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0); in lpphy_baseband_rev2plus_init()
420 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10); in lpphy_baseband_rev2plus_init()
421 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4); in lpphy_baseband_rev2plus_init()
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200); in lpphy_baseband_rev2plus_init()
423 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F); in lpphy_baseband_rev2plus_init()
424 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40); in lpphy_baseband_rev2plus_init()
425 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2); in lpphy_baseband_rev2plus_init()
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000); in lpphy_baseband_rev2plus_init()
427 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000); in lpphy_baseband_rev2plus_init()
428 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1); in lpphy_baseband_rev2plus_init()
429 if (dev->dev->board_rev >= 0x18) { in lpphy_baseband_rev2plus_init()
430 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC); in lpphy_baseband_rev2plus_init()
431 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14); in lpphy_baseband_rev2plus_init()
433 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10); in lpphy_baseband_rev2plus_init()
435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4); in lpphy_baseband_rev2plus_init()
436 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100); in lpphy_baseband_rev2plus_init()
437 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48); in lpphy_baseband_rev2plus_init()
438 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46); in lpphy_baseband_rev2plus_init()
439 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10); in lpphy_baseband_rev2plus_init()
440 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9); in lpphy_baseband_rev2plus_init()
441 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF); in lpphy_baseband_rev2plus_init()
442 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500); in lpphy_baseband_rev2plus_init()
443 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0); in lpphy_baseband_rev2plus_init()
444 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300); in lpphy_baseband_rev2plus_init()
445 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00); in lpphy_baseband_rev2plus_init()
446 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { in lpphy_baseband_rev2plus_init()
447 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100); in lpphy_baseband_rev2plus_init()
448 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA); in lpphy_baseband_rev2plus_init()
450 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00); in lpphy_baseband_rev2plus_init()
451 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD); in lpphy_baseband_rev2plus_init()
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F); in lpphy_baseband_rev2plus_init()
454 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC); in lpphy_baseband_rev2plus_init()
455 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19); in lpphy_baseband_rev2plus_init()
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00); in lpphy_baseband_rev2plus_init()
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0); in lpphy_baseband_rev2plus_init()
458 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC); in lpphy_baseband_rev2plus_init()
459 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900); in lpphy_baseband_rev2plus_init()
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800); in lpphy_baseband_rev2plus_init()
461 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12); in lpphy_baseband_rev2plus_init()
462 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000); in lpphy_baseband_rev2plus_init()
464 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { in lpphy_baseband_rev2plus_init()
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0); in lpphy_baseband_rev2plus_init()
466 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40); in lpphy_baseband_rev2plus_init()
469 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_baseband_rev2plus_init()
470 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40); in lpphy_baseband_rev2plus_init()
471 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00); in lpphy_baseband_rev2plus_init()
472 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6); in lpphy_baseband_rev2plus_init()
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00); in lpphy_baseband_rev2plus_init()
474 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1); in lpphy_baseband_rev2plus_init()
475 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); in lpphy_baseband_rev2plus_init()
477 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40); in lpphy_baseband_rev2plus_init()
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3); in lpphy_baseband_rev2plus_init()
480 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00); in lpphy_baseband_rev2plus_init()
481 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset); in lpphy_baseband_rev2plus_init()
482 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44); in lpphy_baseband_rev2plus_init()
483 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80); in lpphy_baseband_rev2plus_init()
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954); in lpphy_baseband_rev2plus_init()
485 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1, in lpphy_baseband_rev2plus_init()
489 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { in lpphy_baseband_rev2plus_init()
490 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C); in lpphy_baseband_rev2plus_init()
491 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800); in lpphy_baseband_rev2plus_init()
492 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400); in lpphy_baseband_rev2plus_init()
495 lpphy_save_dig_flt_state(dev); in lpphy_baseband_rev2plus_init()
498 static void lpphy_baseband_init(struct b43_wldev *dev) in lpphy_baseband_init() argument
500 lpphy_table_init(dev); in lpphy_baseband_init()
501 if (dev->phy.rev >= 2) in lpphy_baseband_init()
502 lpphy_baseband_rev2plus_init(dev); in lpphy_baseband_init()
504 lpphy_baseband_rev0_1_init(dev); in lpphy_baseband_init()
513 static void lpphy_2062_init(struct b43_wldev *dev) in lpphy_2062_init() argument
515 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_2062_init()
516 struct ssb_bus *bus = dev->dev->sdev->bus; in lpphy_2062_init()
536 b2062_upload_init_table(dev); in lpphy_2062_init()
538 b43_radio_write(dev, B2062_N_TX_CTL3, 0); in lpphy_2062_init()
539 b43_radio_write(dev, B2062_N_TX_CTL4, 0); in lpphy_2062_init()
540 b43_radio_write(dev, B2062_N_TX_CTL5, 0); in lpphy_2062_init()
541 b43_radio_write(dev, B2062_N_TX_CTL6, 0); in lpphy_2062_init()
542 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40); in lpphy_2062_init()
543 b43_radio_write(dev, B2062_N_PDN_CTL0, 0); in lpphy_2062_init()
544 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10); in lpphy_2062_init()
545 b43_radio_write(dev, B2062_N_CALIB_TS, 0); in lpphy_2062_init()
546 if (dev->phy.rev > 0) { in lpphy_2062_init()
547 b43_radio_write(dev, B2062_S_BG_CTL1, in lpphy_2062_init()
548 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80); in lpphy_2062_init()
550 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in lpphy_2062_init()
551 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1); in lpphy_2062_init()
553 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1); in lpphy_2062_init()
563 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB); in lpphy_2062_init()
566 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4); in lpphy_2062_init()
571 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp); in lpphy_2062_init()
575 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp); in lpphy_2062_init()
579 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp); in lpphy_2062_init()
591 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n", in lpphy_2062_init()
594 b43_radio_write(dev, B2062_S_RFPLL_CTL8, in lpphy_2062_init()
596 b43_radio_write(dev, B2062_S_RFPLL_CTL9, in lpphy_2062_init()
598 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]); in lpphy_2062_init()
599 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]); in lpphy_2062_init()
603 static void lpphy_2063_init(struct b43_wldev *dev) in lpphy_2063_init() argument
605 b2063_upload_init_table(dev); in lpphy_2063_init()
606 b43_radio_write(dev, B2063_LOGEN_SP5, 0); in lpphy_2063_init()
607 b43_radio_set(dev, B2063_COMM8, 0x38); in lpphy_2063_init()
608 b43_radio_write(dev, B2063_REG_SP1, 0x56); in lpphy_2063_init()
609 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2); in lpphy_2063_init()
610 b43_radio_write(dev, B2063_PA_SP7, 0); in lpphy_2063_init()
611 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20); in lpphy_2063_init()
612 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40); in lpphy_2063_init()
613 if (dev->phy.rev == 2) { in lpphy_2063_init()
614 b43_radio_write(dev, B2063_PA_SP3, 0xa0); in lpphy_2063_init()
615 b43_radio_write(dev, B2063_PA_SP4, 0xa0); in lpphy_2063_init()
616 b43_radio_write(dev, B2063_PA_SP2, 0x18); in lpphy_2063_init()
618 b43_radio_write(dev, B2063_PA_SP3, 0x20); in lpphy_2063_init()
619 b43_radio_write(dev, B2063_PA_SP2, 0x20); in lpphy_2063_init()
663 static void lpphy_sync_stx(struct b43_wldev *dev) in lpphy_sync_stx() argument
671 tmp = b43_radio_read(dev, e->rf_addr); in lpphy_sync_stx()
674 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset), in lpphy_sync_stx()
679 static void lpphy_radio_init(struct b43_wldev *dev) in lpphy_radio_init() argument
682 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2); in lpphy_radio_init()
684 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD); in lpphy_radio_init()
687 if (dev->phy.radio_ver == 0x2062) { in lpphy_radio_init()
688 lpphy_2062_init(dev); in lpphy_radio_init()
690 lpphy_2063_init(dev); in lpphy_radio_init()
691 lpphy_sync_stx(dev); in lpphy_radio_init()
692 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80); in lpphy_radio_init()
693 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0); in lpphy_radio_init()
694 if (dev->dev->chip_id == 0x4325) { in lpphy_radio_init()
702 static void lpphy_set_rc_cap(struct b43_wldev *dev) in lpphy_set_rc_cap() argument
704 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_set_rc_cap()
708 if (dev->phy.rev == 1) //FIXME check channel 14! in lpphy_set_rc_cap()
711 b43_radio_write(dev, B2062_N_RXBB_CALIB2, in lpphy_set_rc_cap()
713 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80); in lpphy_set_rc_cap()
714 b43_radio_write(dev, B2062_S_RXG_CNT16, in lpphy_set_rc_cap()
718 static u8 lpphy_get_bb_mult(struct b43_wldev *dev) in lpphy_get_bb_mult() argument
720 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8; in lpphy_get_bb_mult()
723 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult) in lpphy_set_bb_mult() argument
725 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8); in lpphy_set_bb_mult()
728 static void lpphy_set_deaf(struct b43_wldev *dev, bool user) in lpphy_set_deaf() argument
730 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_set_deaf()
736 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80); in lpphy_set_deaf()
739 static void lpphy_clear_deaf(struct b43_wldev *dev, bool user) in lpphy_clear_deaf() argument
741 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_clear_deaf()
749 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in lpphy_clear_deaf()
750 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, in lpphy_clear_deaf()
753 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, in lpphy_clear_deaf()
758 static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx) in lpphy_set_trsw_over() argument
761 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw); in lpphy_set_trsw_over()
762 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3); in lpphy_set_trsw_over()
765 static void lpphy_disable_crs(struct b43_wldev *dev, bool user) in lpphy_disable_crs() argument
767 lpphy_set_deaf(dev, user); in lpphy_disable_crs()
768 lpphy_set_trsw_over(dev, false, true); in lpphy_disable_crs()
769 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB); in lpphy_disable_crs()
770 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4); in lpphy_disable_crs()
771 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7); in lpphy_disable_crs()
772 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8); in lpphy_disable_crs()
773 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10); in lpphy_disable_crs()
774 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10); in lpphy_disable_crs()
775 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF); in lpphy_disable_crs()
776 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20); in lpphy_disable_crs()
777 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF); in lpphy_disable_crs()
778 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40); in lpphy_disable_crs()
779 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7); in lpphy_disable_crs()
780 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38); in lpphy_disable_crs()
781 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F); in lpphy_disable_crs()
782 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100); in lpphy_disable_crs()
783 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF); in lpphy_disable_crs()
784 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0); in lpphy_disable_crs()
785 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1); in lpphy_disable_crs()
786 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20); in lpphy_disable_crs()
787 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF); in lpphy_disable_crs()
788 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF); in lpphy_disable_crs()
789 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0); in lpphy_disable_crs()
790 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF); in lpphy_disable_crs()
791 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF); in lpphy_disable_crs()
794 static void lpphy_restore_crs(struct b43_wldev *dev, bool user) in lpphy_restore_crs() argument
796 lpphy_clear_deaf(dev, user); in lpphy_restore_crs()
797 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80); in lpphy_restore_crs()
798 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00); in lpphy_restore_crs()
803 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev) in lpphy_disable_rx_gain_override() argument
805 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE); in lpphy_disable_rx_gain_override()
806 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF); in lpphy_disable_rx_gain_override()
807 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF); in lpphy_disable_rx_gain_override()
808 if (dev->phy.rev >= 2) { in lpphy_disable_rx_gain_override()
809 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_rx_gain_override()
810 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_disable_rx_gain_override()
811 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF); in lpphy_disable_rx_gain_override()
812 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7); in lpphy_disable_rx_gain_override()
815 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF); in lpphy_disable_rx_gain_override()
819 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev) in lpphy_enable_rx_gain_override() argument
821 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1); in lpphy_enable_rx_gain_override()
822 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10); in lpphy_enable_rx_gain_override()
823 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40); in lpphy_enable_rx_gain_override()
824 if (dev->phy.rev >= 2) { in lpphy_enable_rx_gain_override()
825 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100); in lpphy_enable_rx_gain_override()
826 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_enable_rx_gain_override()
827 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400); in lpphy_enable_rx_gain_override()
828 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8); in lpphy_enable_rx_gain_override()
831 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200); in lpphy_enable_rx_gain_override()
835 static void lpphy_disable_tx_gain_override(struct b43_wldev *dev) in lpphy_disable_tx_gain_override() argument
837 if (dev->phy.rev < 2) in lpphy_disable_tx_gain_override()
838 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); in lpphy_disable_tx_gain_override()
840 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F); in lpphy_disable_tx_gain_override()
841 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF); in lpphy_disable_tx_gain_override()
843 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF); in lpphy_disable_tx_gain_override()
846 static void lpphy_enable_tx_gain_override(struct b43_wldev *dev) in lpphy_enable_tx_gain_override() argument
848 if (dev->phy.rev < 2) in lpphy_enable_tx_gain_override()
849 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100); in lpphy_enable_tx_gain_override()
851 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80); in lpphy_enable_tx_gain_override()
852 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000); in lpphy_enable_tx_gain_override()
854 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40); in lpphy_enable_tx_gain_override()
857 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev) in lpphy_get_tx_gains() argument
862 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7; in lpphy_get_tx_gains()
863 if (dev->phy.rev < 2) { in lpphy_get_tx_gains()
864 tmp = b43_phy_read(dev, in lpphy_get_tx_gains()
870 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL); in lpphy_get_tx_gains()
871 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF; in lpphy_get_tx_gains()
879 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac) in lpphy_set_dac_gain() argument
881 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F; in lpphy_set_dac_gain()
883 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl); in lpphy_set_dac_gain()
886 static u16 lpphy_get_pa_gain(struct b43_wldev *dev) in lpphy_get_pa_gain() argument
888 return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F; in lpphy_get_pa_gain()
891 static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain) in lpphy_set_pa_gain() argument
893 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6); in lpphy_set_pa_gain()
894 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8); in lpphy_set_pa_gain()
897 static void lpphy_set_tx_gains(struct b43_wldev *dev, in lpphy_set_tx_gains() argument
902 if (dev->phy.rev < 2) { in lpphy_set_tx_gains()
904 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, in lpphy_set_tx_gains()
907 pa_gain = lpphy_get_pa_gain(dev); in lpphy_set_tx_gains()
908 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, in lpphy_set_tx_gains()
914 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), in lpphy_set_tx_gains()
916 b43_phy_write(dev, B43_PHY_OFDM(0xFC), in lpphy_set_tx_gains()
918 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), in lpphy_set_tx_gains()
921 lpphy_set_dac_gain(dev, gains.dac); in lpphy_set_tx_gains()
922 lpphy_enable_tx_gain_override(dev); in lpphy_set_tx_gains()
925 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain) in lpphy_rev0_1_set_rx_gain() argument
931 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw); in lpphy_rev0_1_set_rx_gain()
932 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, in lpphy_rev0_1_set_rx_gain()
934 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, in lpphy_rev0_1_set_rx_gain()
936 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna); in lpphy_rev0_1_set_rx_gain()
939 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain) in lpphy_rev2plus_set_rx_gain() argument
947 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw); in lpphy_rev2plus_set_rx_gain()
948 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, in lpphy_rev2plus_set_rx_gain()
950 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, in lpphy_rev2plus_set_rx_gain()
952 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain); in lpphy_rev2plus_set_rx_gain()
953 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain); in lpphy_rev2plus_set_rx_gain()
954 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_rev2plus_set_rx_gain()
956 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, in lpphy_rev2plus_set_rx_gain()
958 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3); in lpphy_rev2plus_set_rx_gain()
962 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain) in lpphy_set_rx_gain() argument
964 if (dev->phy.rev < 2) in lpphy_set_rx_gain()
965 lpphy_rev0_1_set_rx_gain(dev, gain); in lpphy_set_rx_gain()
967 lpphy_rev2plus_set_rx_gain(dev, gain); in lpphy_set_rx_gain()
968 lpphy_enable_rx_gain_override(dev); in lpphy_set_rx_gain()
971 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx) in lpphy_set_rx_gain_by_index() argument
973 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx)); in lpphy_set_rx_gain_by_index()
974 lpphy_set_rx_gain(dev, gain); in lpphy_set_rx_gain_by_index()
977 static void lpphy_stop_ddfs(struct b43_wldev *dev) in lpphy_stop_ddfs() argument
979 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD); in lpphy_stop_ddfs()
980 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF); in lpphy_stop_ddfs()
983 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on, in lpphy_run_ddfs() argument
986 lpphy_stop_ddfs(dev); in lpphy_run_ddfs()
987 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80); in lpphy_run_ddfs()
988 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF); in lpphy_run_ddfs()
989 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1); in lpphy_run_ddfs()
990 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8); in lpphy_run_ddfs()
991 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3); in lpphy_run_ddfs()
992 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4); in lpphy_run_ddfs()
993 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5); in lpphy_run_ddfs()
994 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB); in lpphy_run_ddfs()
995 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2); in lpphy_run_ddfs()
996 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20); in lpphy_run_ddfs()
999 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time, in lpphy_rx_iq_est() argument
1004 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7); in lpphy_rx_iq_est()
1005 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples); in lpphy_rx_iq_est()
1006 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time); in lpphy_rx_iq_est()
1007 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF); in lpphy_rx_iq_est()
1008 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200); in lpphy_rx_iq_est()
1011 if (!(b43_phy_read(dev, in lpphy_rx_iq_est()
1017 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) { in lpphy_rx_iq_est()
1018 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8); in lpphy_rx_iq_est()
1022 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR); in lpphy_rx_iq_est()
1024 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR); in lpphy_rx_iq_est()
1026 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR); in lpphy_rx_iq_est()
1028 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR); in lpphy_rx_iq_est()
1030 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR); in lpphy_rx_iq_est()
1032 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR); in lpphy_rx_iq_est()
1034 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8); in lpphy_rx_iq_est()
1038 static int lpphy_loopback(struct b43_wldev *dev) in lpphy_loopback() argument
1046 lpphy_set_trsw_over(dev, true, true); in lpphy_loopback()
1047 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1); in lpphy_loopback()
1048 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_loopback()
1049 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800); in lpphy_loopback()
1050 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800); in lpphy_loopback()
1051 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8); in lpphy_loopback()
1052 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8); in lpphy_loopback()
1053 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80); in lpphy_loopback()
1054 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80); in lpphy_loopback()
1055 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80); in lpphy_loopback()
1057 lpphy_set_rx_gain_by_index(dev, i); in lpphy_loopback()
1058 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0); in lpphy_loopback()
1059 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est))) in lpphy_loopback()
1067 lpphy_stop_ddfs(dev); in lpphy_loopback()
1098 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev) in lpphy_read_tx_pctl_mode_from_hardware() argument
1100 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_read_tx_pctl_mode_from_hardware()
1103 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD); in lpphy_read_tx_pctl_mode_from_hardware()
1122 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev) in lpphy_write_tx_pctl_mode_to_hardware() argument
1124 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_write_tx_pctl_mode_to_hardware()
1141 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, in lpphy_write_tx_pctl_mode_to_hardware()
1145 static void lpphy_set_tx_power_control(struct b43_wldev *dev, in lpphy_set_tx_power_control() argument
1148 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_set_tx_power_control()
1151 lpphy_read_tx_pctl_mode_from_hardware(dev); in lpphy_set_tx_power_control()
1163 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, in lpphy_set_tx_power_control()
1165 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, in lpphy_set_tx_power_control()
1168 lpphy_disable_tx_gain_override(dev); in lpphy_set_tx_power_control()
1172 if (dev->phy.rev >= 2) { in lpphy_set_tx_power_control()
1174 b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2); in lpphy_set_tx_power_control()
1176 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD); in lpphy_set_tx_power_control()
1178 lpphy_write_tx_pctl_mode_to_hardware(dev); in lpphy_set_tx_power_control()
1181 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1184 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev) in lpphy_rev0_1_rc_calib() argument
1186 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_rev0_1_rc_calib()
1205 err = b43_lpphy_op_switch_channel(dev, 7); in lpphy_rev0_1_rc_calib()
1207 b43dbg(dev->wl, in lpphy_rev0_1_rc_calib()
1211 old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40); in lpphy_rev0_1_rc_calib()
1212 old_bbmult = lpphy_get_bb_mult(dev); in lpphy_rev0_1_rc_calib()
1214 tx_gains = lpphy_get_tx_gains(dev); in lpphy_rev0_1_rc_calib()
1215 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0); in lpphy_rev0_1_rc_calib()
1216 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0); in lpphy_rev0_1_rc_calib()
1217 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR); in lpphy_rev0_1_rc_calib()
1218 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL); in lpphy_rev0_1_rc_calib()
1219 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2); in lpphy_rev0_1_rc_calib()
1220 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL); in lpphy_rev0_1_rc_calib()
1221 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL); in lpphy_rev0_1_rc_calib()
1222 lpphy_read_tx_pctl_mode_from_hardware(dev); in lpphy_rev0_1_rc_calib()
1225 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); in lpphy_rev0_1_rc_calib()
1226 lpphy_disable_crs(dev, true); in lpphy_rev0_1_rc_calib()
1227 loopback = lpphy_loopback(dev); in lpphy_rev0_1_rc_calib()
1230 lpphy_set_rx_gain_by_index(dev, loopback); in lpphy_rev0_1_rc_calib()
1231 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40); in lpphy_rev0_1_rc_calib()
1232 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1); in lpphy_rev0_1_rc_calib()
1233 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8); in lpphy_rev0_1_rc_calib()
1234 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0); in lpphy_rev0_1_rc_calib()
1236 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i); in lpphy_rev0_1_rc_calib()
1239 lpphy_run_ddfs(dev, 1, 1, j, j, 0); in lpphy_rev0_1_rc_calib()
1240 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est))) in lpphy_rev0_1_rc_calib()
1256 lpphy_stop_ddfs(dev); in lpphy_rev0_1_rc_calib()
1259 lpphy_restore_crs(dev, true); in lpphy_rev0_1_rc_calib()
1260 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval); in lpphy_rev0_1_rc_calib()
1261 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr); in lpphy_rev0_1_rc_calib()
1262 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval); in lpphy_rev0_1_rc_calib()
1263 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr); in lpphy_rev0_1_rc_calib()
1264 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval); in lpphy_rev0_1_rc_calib()
1265 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr); in lpphy_rev0_1_rc_calib()
1266 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl); in lpphy_rev0_1_rc_calib()
1268 lpphy_set_bb_mult(dev, old_bbmult); in lpphy_rev0_1_rc_calib()
1277 lpphy_set_tx_gains(dev, tx_gains); in lpphy_rev0_1_rc_calib()
1279 lpphy_set_tx_power_control(dev, old_txpctl); in lpphy_rev0_1_rc_calib()
1281 lpphy_set_rc_cap(dev); in lpphy_rev0_1_rc_calib()
1284 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev) in lpphy_rev2plus_rc_calib() argument
1286 struct ssb_bus *bus = dev->dev->sdev->bus; in lpphy_rev2plus_rc_calib()
1288 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF; in lpphy_rev2plus_rc_calib()
1291 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0); in lpphy_rev2plus_rc_calib()
1292 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E); in lpphy_rev2plus_rc_calib()
1293 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7); in lpphy_rev2plus_rc_calib()
1294 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C); in lpphy_rev2plus_rc_calib()
1295 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15); in lpphy_rev2plus_rc_calib()
1296 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70); in lpphy_rev2plus_rc_calib()
1297 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52); in lpphy_rev2plus_rc_calib()
1298 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1); in lpphy_rev2plus_rc_calib()
1299 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D); in lpphy_rev2plus_rc_calib()
1302 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2) in lpphy_rev2plus_rc_calib()
1307 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)) in lpphy_rev2plus_rc_calib()
1308 b43_radio_write(dev, B2063_RX_BB_SP8, tmp); in lpphy_rev2plus_rc_calib()
1310 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF; in lpphy_rev2plus_rc_calib()
1312 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0); in lpphy_rev2plus_rc_calib()
1313 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E); in lpphy_rev2plus_rc_calib()
1314 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C); in lpphy_rev2plus_rc_calib()
1315 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55); in lpphy_rev2plus_rc_calib()
1316 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76); in lpphy_rev2plus_rc_calib()
1319 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC); in lpphy_rev2plus_rc_calib()
1320 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0); in lpphy_rev2plus_rc_calib()
1322 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13); in lpphy_rev2plus_rc_calib()
1323 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1); in lpphy_rev2plus_rc_calib()
1326 b43_radio_write(dev, B2063_PA_SP7, 0x7D); in lpphy_rev2plus_rc_calib()
1329 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2) in lpphy_rev2plus_rc_calib()
1334 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)) in lpphy_rev2plus_rc_calib()
1335 b43_radio_write(dev, B2063_TX_BB_SP3, tmp); in lpphy_rev2plus_rc_calib()
1337 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E); in lpphy_rev2plus_rc_calib()
1340 static void lpphy_calibrate_rc(struct b43_wldev *dev) in lpphy_calibrate_rc() argument
1342 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_calibrate_rc()
1344 if (dev->phy.rev >= 2) { in lpphy_calibrate_rc()
1345 lpphy_rev2plus_rc_calib(dev); in lpphy_calibrate_rc()
1347 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) in lpphy_calibrate_rc()
1348 lpphy_rev0_1_rc_calib(dev); in lpphy_calibrate_rc()
1350 lpphy_set_rc_cap(dev); in lpphy_calibrate_rc()
1354 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) in b43_lpphy_op_set_rx_antenna() argument
1356 if (dev->phy.rev >= 2) in b43_lpphy_op_set_rx_antenna()
1362 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); in b43_lpphy_op_set_rx_antenna()
1364 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2); in b43_lpphy_op_set_rx_antenna()
1365 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1); in b43_lpphy_op_set_rx_antenna()
1367 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); in b43_lpphy_op_set_rx_antenna()
1369 dev->phy.lp->antenna = antenna; in b43_lpphy_op_set_rx_antenna()
1372 static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b) in lpphy_set_tx_iqcc() argument
1378 b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp); in lpphy_set_tx_iqcc()
1381 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index) in lpphy_set_tx_power_by_index() argument
1383 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_set_tx_power_by_index()
1388 lpphy_read_tx_pctl_mode_from_hardware(dev); in lpphy_set_tx_power_by_index()
1390 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW); in lpphy_set_tx_power_by_index()
1391 if (dev->phy.rev >= 2) { in lpphy_set_tx_power_by_index()
1392 iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320)); in lpphy_set_tx_power_by_index()
1393 tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192)); in lpphy_set_tx_power_by_index()
1398 lpphy_set_tx_gains(dev, gains); in lpphy_set_tx_power_by_index()
1400 iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320)); in lpphy_set_tx_power_by_index()
1401 tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192)); in lpphy_set_tx_power_by_index()
1402 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, in lpphy_set_tx_power_by_index()
1404 lpphy_set_dac_gain(dev, tx_gain & 0x7); in lpphy_set_tx_power_by_index()
1405 lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F); in lpphy_set_tx_power_by_index()
1407 lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF); in lpphy_set_tx_power_by_index()
1408 lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF); in lpphy_set_tx_power_by_index()
1409 if (dev->phy.rev >= 2) { in lpphy_set_tx_power_by_index()
1410 coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448)); in lpphy_set_tx_power_by_index()
1412 coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448)); in lpphy_set_tx_power_by_index()
1414 b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF); in lpphy_set_tx_power_by_index()
1415 if (dev->phy.rev >= 2) { in lpphy_set_tx_power_by_index()
1416 rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576)); in lpphy_set_tx_power_by_index()
1417 b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, in lpphy_set_tx_power_by_index()
1420 lpphy_enable_tx_gain_override(dev); in lpphy_set_tx_power_by_index()
1423 static void lpphy_btcoex_override(struct b43_wldev *dev) in lpphy_btcoex_override() argument
1425 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3); in lpphy_btcoex_override()
1426 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF); in lpphy_btcoex_override()
1429 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev, in b43_lpphy_op_software_rfkill() argument
1434 if (dev->phy.rev >= 2) { in b43_lpphy_op_software_rfkill()
1435 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF); in b43_lpphy_op_software_rfkill()
1436 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00); in b43_lpphy_op_software_rfkill()
1437 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF); in b43_lpphy_op_software_rfkill()
1438 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF); in b43_lpphy_op_software_rfkill()
1439 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808); in b43_lpphy_op_software_rfkill()
1441 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1442 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00); in b43_lpphy_op_software_rfkill()
1443 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF); in b43_lpphy_op_software_rfkill()
1444 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018); in b43_lpphy_op_software_rfkill()
1447 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF); in b43_lpphy_op_software_rfkill()
1448 if (dev->phy.rev >= 2) in b43_lpphy_op_software_rfkill()
1449 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7); in b43_lpphy_op_software_rfkill()
1451 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7); in b43_lpphy_op_software_rfkill()
1456 static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel) in lpphy_set_analog_filter() argument
1458 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_set_analog_filter()
1461 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific? in lpphy_set_analog_filter()
1462 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9); in lpphy_set_analog_filter()
1463 if ((dev->phy.rev == 1) && (lpphy->rc_cap)) in lpphy_set_analog_filter()
1464 lpphy_set_rc_cap(dev); in lpphy_set_analog_filter()
1466 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F); in lpphy_set_analog_filter()
1470 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode) in lpphy_set_tssi_mux() argument
1473 b43_radio_set(dev, B2063_PA_SP1, 0x2); in lpphy_set_tssi_mux()
1474 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000); in lpphy_set_tssi_mux()
1475 b43_radio_write(dev, B2063_PA_CTL10, 0x51); in lpphy_set_tssi_mux()
1477 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE); in lpphy_set_tssi_mux()
1478 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7); in lpphy_set_tssi_mux()
1480 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1); in lpphy_set_tssi_mux()
1481 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL, in lpphy_set_tssi_mux()
1489 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev) in lpphy_tx_pctl_init_hw() argument
1496 if (dev->phy.rev >= 2) in lpphy_tx_pctl_init_hw()
1497 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i); in lpphy_tx_pctl_init_hw()
1499 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i); in lpphy_tx_pctl_init_hw()
1502 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF); in lpphy_tx_pctl_init_hw()
1503 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000); in lpphy_tx_pctl_init_hw()
1504 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F); in lpphy_tx_pctl_init_hw()
1505 if (dev->phy.rev < 2) { in lpphy_tx_pctl_init_hw()
1506 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF); in lpphy_tx_pctl_init_hw()
1507 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000); in lpphy_tx_pctl_init_hw()
1509 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE); in lpphy_tx_pctl_init_hw()
1510 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4); in lpphy_tx_pctl_init_hw()
1511 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10); in lpphy_tx_pctl_init_hw()
1512 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1); in lpphy_tx_pctl_init_hw()
1513 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA); in lpphy_tx_pctl_init_hw()
1515 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000); in lpphy_tx_pctl_init_hw()
1516 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF); in lpphy_tx_pctl_init_hw()
1517 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA); in lpphy_tx_pctl_init_hw()
1518 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, in lpphy_tx_pctl_init_hw()
1521 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF); in lpphy_tx_pctl_init_hw()
1522 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, in lpphy_tx_pctl_init_hw()
1526 if (dev->phy.rev < 2) { in lpphy_tx_pctl_init_hw()
1527 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000); in lpphy_tx_pctl_init_hw()
1528 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1530 lpphy_set_tx_power_by_index(dev, 0x7F); in lpphy_tx_pctl_init_hw()
1533 b43_dummy_transmission(dev, true, true); in lpphy_tx_pctl_init_hw()
1535 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT); in lpphy_tx_pctl_init_hw()
1537 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, in lpphy_tx_pctl_init_hw()
1541 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF); in lpphy_tx_pctl_init_hw()
1547 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev) in lpphy_tx_pctl_init_sw() argument
1551 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_tx_pctl_init_sw()
1562 lpphy_set_tx_gains(dev, gains); in lpphy_tx_pctl_init_sw()
1563 lpphy_set_bb_mult(dev, 150); in lpphy_tx_pctl_init_sw()
1567 static void lpphy_tx_pctl_init(struct b43_wldev *dev) in lpphy_tx_pctl_init() argument
1570 lpphy_tx_pctl_init_hw(dev); in lpphy_tx_pctl_init()
1572 lpphy_tx_pctl_init_sw(dev); in lpphy_tx_pctl_init()
1576 static void lpphy_pr41573_workaround(struct b43_wldev *dev) in lpphy_pr41573_workaround() argument
1578 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_pr41573_workaround()
1587 b43err(dev->wl, "PR41573 failed. Out of memory!\n"); in lpphy_pr41573_workaround()
1591 lpphy_read_tx_pctl_mode_from_hardware(dev); in lpphy_pr41573_workaround()
1597 if (dev->phy.rev < 2) { in lpphy_pr41573_workaround()
1598 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140), in lpphy_pr41573_workaround()
1601 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140), in lpphy_pr41573_workaround()
1605 lpphy_table_init(dev); //FIXME is table init needed? in lpphy_pr41573_workaround()
1606 lpphy_baseband_init(dev); in lpphy_pr41573_workaround()
1607 lpphy_tx_pctl_init(dev); in lpphy_pr41573_workaround()
1608 b43_lpphy_op_software_rfkill(dev, false); in lpphy_pr41573_workaround()
1609 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); in lpphy_pr41573_workaround()
1610 if (dev->phy.rev < 2) { in lpphy_pr41573_workaround()
1611 b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140), in lpphy_pr41573_workaround()
1614 b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140), in lpphy_pr41573_workaround()
1617 b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel); in lpphy_pr41573_workaround()
1620 lpphy_set_analog_filter(dev, lpphy->channel); in lpphy_pr41573_workaround()
1622 lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over); in lpphy_pr41573_workaround()
1624 lpphy_set_rc_cap(dev); in lpphy_pr41573_workaround()
1625 b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna); in lpphy_pr41573_workaround()
1626 lpphy_set_tx_power_control(dev, txpctl_mode); in lpphy_pr41573_workaround()
1709 static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples) in lpphy_calc_rx_iq_comp() argument
1715 c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S); in lpphy_calc_rx_iq_comp()
1719 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0); in lpphy_calc_rx_iq_comp()
1720 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF); in lpphy_calc_rx_iq_comp()
1722 ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est); in lpphy_calc_rx_iq_comp()
1761 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1); in lpphy_calc_rx_iq_comp()
1762 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8); in lpphy_calc_rx_iq_comp()
1766 static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops, in lpphy_run_samples() argument
1769 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, in lpphy_run_samples()
1773 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops); in lpphy_run_samples()
1774 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6); in lpphy_run_samples()
1775 b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1); in lpphy_run_samples()
1779 static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max) in lpphy_start_tx_tone() argument
1781 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_start_tx_tone()
1807 b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf); in lpphy_start_tx_tone()
1809 lpphy_run_samples(dev, samples, 0xFFFF, 0); in lpphy_start_tx_tone()
1812 static void lpphy_stop_tx_tone(struct b43_wldev *dev) in lpphy_stop_tx_tone() argument
1814 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_stop_tx_tone()
1819 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000); in lpphy_stop_tx_tone()
1821 if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1)) in lpphy_stop_tx_tone()
1828 static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains, in lpphy_papd_cal() argument
1834 static void lpphy_papd_cal_txpwr(struct b43_wldev *dev) in lpphy_papd_cal_txpwr() argument
1836 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_papd_cal_txpwr()
1840 lpphy_read_tx_pctl_mode_from_hardware(dev); in lpphy_papd_cal_txpwr()
1842 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40; in lpphy_papd_cal_txpwr()
1844 oldgains = lpphy_get_tx_gains(dev); in lpphy_papd_cal_txpwr()
1845 old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF; in lpphy_papd_cal_txpwr()
1846 old_bbmult = lpphy_get_bb_mult(dev); in lpphy_papd_cal_txpwr()
1848 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); in lpphy_papd_cal_txpwr()
1850 if (dev->dev->chip_id == 0x4325 && dev->dev->chip_rev == 0) in lpphy_papd_cal_txpwr()
1851 lpphy_papd_cal(dev, gains, 0, 1, 30); in lpphy_papd_cal_txpwr()
1853 lpphy_papd_cal(dev, gains, 0, 1, 65); in lpphy_papd_cal_txpwr()
1856 lpphy_set_tx_gains(dev, oldgains); in lpphy_papd_cal_txpwr()
1857 lpphy_set_bb_mult(dev, old_bbmult); in lpphy_papd_cal_txpwr()
1858 lpphy_set_tx_power_control(dev, old_txpctl); in lpphy_papd_cal_txpwr()
1859 b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf); in lpphy_papd_cal_txpwr()
1862 static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx, in lpphy_rx_iq_cal() argument
1865 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_rx_iq_cal()
1874 if (dev->dev->chip_id == 0x5354) { in lpphy_rx_iq_cal()
1880 } else if (dev->phy.rev >= 2) { in lpphy_rx_iq_cal()
1893 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1); in lpphy_rx_iq_cal()
1894 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, in lpphy_rx_iq_cal()
1903 lpphy_set_trsw_over(dev, tx, rx); in lpphy_rx_iq_cal()
1905 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { in lpphy_rx_iq_cal()
1906 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8); in lpphy_rx_iq_cal()
1907 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, in lpphy_rx_iq_cal()
1910 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20); in lpphy_rx_iq_cal()
1911 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, in lpphy_rx_iq_cal()
1915 tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40; in lpphy_rx_iq_cal()
1918 lpphy_set_rx_gain(dev, 0x2D5D); in lpphy_rx_iq_cal()
1921 oldgains = lpphy_get_tx_gains(dev); in lpphy_rx_iq_cal()
1924 lpphy_set_tx_gains(dev, *gains); in lpphy_rx_iq_cal()
1927 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1928 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); in lpphy_rx_iq_cal()
1929 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800); in lpphy_rx_iq_cal()
1930 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800); in lpphy_rx_iq_cal()
1931 lpphy_set_deaf(dev, false); in lpphy_rx_iq_cal()
1933 ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0); in lpphy_rx_iq_cal()
1935 lpphy_start_tx_tone(dev, 4000, 100); in lpphy_rx_iq_cal()
1936 ret = lpphy_calc_rx_iq_comp(dev, 0x4000); in lpphy_rx_iq_cal()
1937 lpphy_stop_tx_tone(dev); in lpphy_rx_iq_cal()
1939 lpphy_clear_deaf(dev, false); in lpphy_rx_iq_cal()
1940 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC); in lpphy_rx_iq_cal()
1941 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7); in lpphy_rx_iq_cal()
1942 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF); in lpphy_rx_iq_cal()
1945 lpphy_set_tx_gains(dev, oldgains); in lpphy_rx_iq_cal()
1947 lpphy_disable_tx_gain_override(dev); in lpphy_rx_iq_cal()
1949 lpphy_disable_rx_gain_override(dev); in lpphy_rx_iq_cal()
1950 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); in lpphy_rx_iq_cal()
1951 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF); in lpphy_rx_iq_cal()
1955 static void lpphy_calibration(struct b43_wldev *dev) in lpphy_calibration() argument
1957 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_calibration()
1966 b43_mac_suspend(dev); in lpphy_calibration()
1968 lpphy_btcoex_override(dev); in lpphy_calibration()
1969 if (dev->phy.rev >= 2) in lpphy_calibration()
1970 lpphy_save_dig_flt_state(dev); in lpphy_calibration()
1971 lpphy_read_tx_pctl_mode_from_hardware(dev); in lpphy_calibration()
1973 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); in lpphy_calibration()
1975 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF)) in lpphy_calibration()
1976 lpphy_pr41573_workaround(dev); in lpphy_calibration()
1977 if ((dev->phy.rev >= 2) && full_cal) { in lpphy_calibration()
1978 lpphy_papd_cal_txpwr(dev); in lpphy_calibration()
1980 lpphy_set_tx_power_control(dev, saved_pctl_mode); in lpphy_calibration()
1981 if (dev->phy.rev >= 2) in lpphy_calibration()
1982 lpphy_restore_dig_flt_state(dev); in lpphy_calibration()
1983 lpphy_rx_iq_cal(dev, true, true, false, false, NULL); in lpphy_calibration()
1985 b43_mac_enable(dev); in lpphy_calibration()
1988 static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, in b43_lpphy_op_maskset() argument
1991 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_lpphy_op_maskset()
1992 b43_write16(dev, B43_MMIO_PHY_DATA, in b43_lpphy_op_maskset()
1993 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); in b43_lpphy_op_maskset()
1996 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_lpphy_op_radio_read() argument
2001 if (dev->phy.rev < 2) { in b43_lpphy_op_radio_read()
2007 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_lpphy_op_radio_read()
2008 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_lpphy_op_radio_read()
2011 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_lpphy_op_radio_write() argument
2016 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_lpphy_op_radio_write()
2017 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_lpphy_op_radio_write()
2389 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev) in lpphy_b2062_reset_pll_bias() argument
2391 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF); in lpphy_b2062_reset_pll_bias()
2393 if (dev->dev->chip_id == 0x5354) { in lpphy_b2062_reset_pll_bias()
2394 b43_radio_write(dev, B2062_N_COMM1, 4); in lpphy_b2062_reset_pll_bias()
2395 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4); in lpphy_b2062_reset_pll_bias()
2397 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0); in lpphy_b2062_reset_pll_bias()
2402 static void lpphy_b2062_vco_calib(struct b43_wldev *dev) in lpphy_b2062_vco_calib() argument
2404 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42); in lpphy_b2062_vco_calib()
2405 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62); in lpphy_b2062_vco_calib()
2409 static int lpphy_b2062_tune(struct b43_wldev *dev, in lpphy_b2062_tune() argument
2412 struct b43_phy_lp *lpphy = dev->phy.lp; in lpphy_b2062_tune()
2413 struct ssb_bus *bus = dev->dev->sdev->bus; in lpphy_b2062_tune()
2429 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04); in lpphy_b2062_tune()
2430 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]); in lpphy_b2062_tune()
2431 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]); in lpphy_b2062_tune()
2432 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]); in lpphy_b2062_tune()
2433 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]); in lpphy_b2062_tune()
2434 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]); in lpphy_b2062_tune()
2435 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]); in lpphy_b2062_tune()
2436 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]); in lpphy_b2062_tune()
2437 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]); in lpphy_b2062_tune()
2438 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]); in lpphy_b2062_tune()
2442 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC); in lpphy_b2062_tune()
2443 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07); in lpphy_b2062_tune()
2444 lpphy_b2062_reset_pll_bias(dev); in lpphy_b2062_tune()
2451 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6); in lpphy_b2062_tune()
2455 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6); in lpphy_b2062_tune()
2459 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6); in lpphy_b2062_tune()
2463 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4)); in lpphy_b2062_tune()
2464 tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19); in lpphy_b2062_tune()
2466 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16); in lpphy_b2062_tune()
2467 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF); in lpphy_b2062_tune()
2469 lpphy_b2062_vco_calib(dev); in lpphy_b2062_tune()
2470 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) { in lpphy_b2062_tune()
2471 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC); in lpphy_b2062_tune()
2472 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0); in lpphy_b2062_tune()
2473 lpphy_b2062_reset_pll_bias(dev); in lpphy_b2062_tune()
2474 lpphy_b2062_vco_calib(dev); in lpphy_b2062_tune()
2475 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) in lpphy_b2062_tune()
2479 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04); in lpphy_b2062_tune()
2483 static void lpphy_b2063_vco_calib(struct b43_wldev *dev) in lpphy_b2063_vco_calib() argument
2487 b43_radio_mask(dev, B2063_PLL_SP1, ~0x40); in lpphy_b2063_vco_calib()
2488 tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8; in lpphy_b2063_vco_calib()
2489 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp); in lpphy_b2063_vco_calib()
2491 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4); in lpphy_b2063_vco_calib()
2493 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6); in lpphy_b2063_vco_calib()
2495 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7); in lpphy_b2063_vco_calib()
2497 b43_radio_set(dev, B2063_PLL_SP1, 0x40); in lpphy_b2063_vco_calib()
2500 static int lpphy_b2063_tune(struct b43_wldev *dev, in lpphy_b2063_tune() argument
2503 struct ssb_bus *bus = dev->dev->sdev->bus; in lpphy_b2063_tune()
2522 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]); in lpphy_b2063_tune()
2523 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]); in lpphy_b2063_tune()
2524 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]); in lpphy_b2063_tune()
2525 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]); in lpphy_b2063_tune()
2526 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]); in lpphy_b2063_tune()
2527 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]); in lpphy_b2063_tune()
2528 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]); in lpphy_b2063_tune()
2529 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]); in lpphy_b2063_tune()
2530 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]); in lpphy_b2063_tune()
2531 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]); in lpphy_b2063_tune()
2532 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]); in lpphy_b2063_tune()
2533 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]); in lpphy_b2063_tune()
2535 old_comm15 = b43_radio_read(dev, B2063_COMM15); in lpphy_b2063_tune()
2536 b43_radio_set(dev, B2063_COMM15, 0x1E); in lpphy_b2063_tune()
2548 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2); in lpphy_b2063_tune()
2549 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6, in lpphy_b2063_tune()
2551 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7, in lpphy_b2063_tune()
2556 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref); in lpphy_b2063_tune()
2561 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7, in lpphy_b2063_tune()
2563 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF); in lpphy_b2063_tune()
2571 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4); in lpphy_b2063_tune()
2572 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4); in lpphy_b2063_tune()
2573 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16); in lpphy_b2063_tune()
2574 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF); in lpphy_b2063_tune()
2575 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF); in lpphy_b2063_tune()
2577 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9); in lpphy_b2063_tune()
2578 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88); in lpphy_b2063_tune()
2579 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28); in lpphy_b2063_tune()
2580 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63); in lpphy_b2063_tune()
2592 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5); in lpphy_b2063_tune()
2593 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6); in lpphy_b2063_tune()
2600 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6); in lpphy_b2063_tune()
2601 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5); in lpphy_b2063_tune()
2603 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4); in lpphy_b2063_tune()
2605 b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2); in lpphy_b2063_tune()
2607 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD); in lpphy_b2063_tune()
2610 b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2); in lpphy_b2063_tune()
2612 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD); in lpphy_b2063_tune()
2614 b43_radio_set(dev, B2063_PLL_SP2, 0x3); in lpphy_b2063_tune()
2616 b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC); in lpphy_b2063_tune()
2617 lpphy_b2063_vco_calib(dev); in lpphy_b2063_tune()
2618 b43_radio_write(dev, B2063_COMM15, old_comm15); in lpphy_b2063_tune()
2623 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev, in b43_lpphy_op_switch_channel() argument
2626 struct b43_phy_lp *lpphy = dev->phy.lp; in b43_lpphy_op_switch_channel()
2629 if (dev->phy.radio_ver == 0x2063) { in b43_lpphy_op_switch_channel()
2630 err = lpphy_b2063_tune(dev, new_channel); in b43_lpphy_op_switch_channel()
2634 err = lpphy_b2062_tune(dev, new_channel); in b43_lpphy_op_switch_channel()
2637 lpphy_set_analog_filter(dev, new_channel); in b43_lpphy_op_switch_channel()
2638 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel)); in b43_lpphy_op_switch_channel()
2642 b43_write16(dev, B43_MMIO_CHANNEL, new_channel); in b43_lpphy_op_switch_channel()
2647 static int b43_lpphy_op_init(struct b43_wldev *dev) in b43_lpphy_op_init() argument
2651 if (dev->dev->bus_type != B43_BUS_SSB) { in b43_lpphy_op_init()
2652 b43err(dev->wl, "LP-PHY is supported only on SSB!\n"); in b43_lpphy_op_init()
2656 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs? in b43_lpphy_op_init()
2657 lpphy_baseband_init(dev); in b43_lpphy_op_init()
2658 lpphy_radio_init(dev); in b43_lpphy_op_init()
2659 lpphy_calibrate_rc(dev); in b43_lpphy_op_init()
2660 err = b43_lpphy_op_switch_channel(dev, 7); in b43_lpphy_op_init()
2662 b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n", in b43_lpphy_op_init()
2665 lpphy_tx_pctl_init(dev); in b43_lpphy_op_init()
2666 lpphy_calibration(dev); in b43_lpphy_op_init()
2672 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev) in b43_lpphy_op_adjust_txpower() argument
2677 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev, in b43_lpphy_op_recalc_txpower() argument
2684 static void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on) in b43_lpphy_op_switch_analog() argument
2687 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8); in b43_lpphy_op_switch_analog()
2689 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0x0007); in b43_lpphy_op_switch_analog()
2690 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x0007); in b43_lpphy_op_switch_analog()
2694 static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev) in b43_lpphy_op_pwork_15sec() argument