48 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,  in b43_radio_2059_channel_setup()  argument
55 	b43_radio_write(dev, 0x16, e->radio_syn16);  in b43_radio_2059_channel_setup()
56 	b43_radio_write(dev, 0x17, e->radio_syn17);  in b43_radio_2059_channel_setup()
57 	b43_radio_write(dev, 0x22, e->radio_syn22);  in b43_radio_2059_channel_setup()
58 	b43_radio_write(dev, 0x25, e->radio_syn25);  in b43_radio_2059_channel_setup()
59 	b43_radio_write(dev, 0x27, e->radio_syn27);  in b43_radio_2059_channel_setup()
60 	b43_radio_write(dev, 0x28, e->radio_syn28);  in b43_radio_2059_channel_setup()
61 	b43_radio_write(dev, 0x29, e->radio_syn29);  in b43_radio_2059_channel_setup()
62 	b43_radio_write(dev, 0x2c, e->radio_syn2c);  in b43_radio_2059_channel_setup()
63 	b43_radio_write(dev, 0x2d, e->radio_syn2d);  in b43_radio_2059_channel_setup()
64 	b43_radio_write(dev, 0x37, e->radio_syn37);  in b43_radio_2059_channel_setup()
65 	b43_radio_write(dev, 0x41, e->radio_syn41);  in b43_radio_2059_channel_setup()
66 	b43_radio_write(dev, 0x43, e->radio_syn43);  in b43_radio_2059_channel_setup()
67 	b43_radio_write(dev, 0x47, e->radio_syn47);  in b43_radio_2059_channel_setup()
71 		b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);  in b43_radio_2059_channel_setup()
72 		b43_radio_write(dev, r | 0x58, e->radio_rxtx58);  in b43_radio_2059_channel_setup()
73 		b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);  in b43_radio_2059_channel_setup()
74 		b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);  in b43_radio_2059_channel_setup()
75 		b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);  in b43_radio_2059_channel_setup()
76 		b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);  in b43_radio_2059_channel_setup()
77 		b43_radio_write(dev, r | 0x92, e->radio_rxtx92);  in b43_radio_2059_channel_setup()
78 		b43_radio_write(dev, r | 0x98, e->radio_rxtx98);  in b43_radio_2059_channel_setup()
84 	b43_radio_mask(dev, R2059_RFPLL_MISC_EN, ~0x1);  in b43_radio_2059_channel_setup()
85 	b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x4);  in b43_radio_2059_channel_setup()
86 	b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4);  in b43_radio_2059_channel_setup()
87 	b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1);  in b43_radio_2059_channel_setup()
93 static void b43_radio_2059_rcal(struct b43_wldev *dev)  in b43_radio_2059_rcal()  argument
96 	b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1);  in b43_radio_2059_rcal()
99 	b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);  in b43_radio_2059_rcal()
100 	b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);  in b43_radio_2059_rcal()
103 	b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2);  in b43_radio_2059_rcal()
107 	b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x2);  in b43_radio_2059_rcal()
109 	if (!b43_radio_wait_value(dev, R2059_C3 | R2059_RCAL_STATUS, 1, 1, 100,  in b43_radio_2059_rcal()
111 		b43err(dev->wl, "Radio 0x2059 rcal timeout\n");  in b43_radio_2059_rcal()
114 	b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x1);  in b43_radio_2059_rcal()
116 	b43_radio_set(dev, 0xa, 0x60);  in b43_radio_2059_rcal()
120 static void b43_radio_2057_rccal(struct b43_wldev *dev)  in b43_radio_2057_rccal()  argument
128 		b43_radio_write(dev, R2059_RCCAL_MASTER, radio_values[i][0]);  in b43_radio_2057_rccal()
129 		b43_radio_write(dev, R2059_RCCAL_X1, 0x6E);  in b43_radio_2057_rccal()
130 		b43_radio_write(dev, R2059_RCCAL_TRC0, radio_values[i][1]);  in b43_radio_2057_rccal()
133 		b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x55);  in b43_radio_2057_rccal()
136 		if (!b43_radio_wait_value(dev, R2059_RCCAL_DONE_OSCCAP, 2, 2,  in b43_radio_2057_rccal()
138 			b43err(dev->wl, "Radio 0x2059 rccal timeout\n");  in b43_radio_2057_rccal()
141 		b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x15);  in b43_radio_2057_rccal()
144 	b43_radio_mask(dev, R2059_RCCAL_MASTER, ~0x1);  in b43_radio_2057_rccal()
147 static void b43_radio_2059_init_pre(struct b43_wldev *dev)  in b43_radio_2059_init_pre()  argument
149 	b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);  in b43_radio_2059_init_pre()
150 	b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_FORCE);  in b43_radio_2059_init_pre()
151 	b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_FORCE);  in b43_radio_2059_init_pre()
152 	b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);  in b43_radio_2059_init_pre()
155 static void b43_radio_2059_init(struct b43_wldev *dev)  in b43_radio_2059_init()  argument
161 	b43_radio_2059_init_pre(dev);  in b43_radio_2059_init()
163 	r2059_upload_inittabs(dev);  in b43_radio_2059_init()
166 		b43_radio_set(dev, routing[i] | 0x146, 0x3);  in b43_radio_2059_init()
170 	b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078);  in b43_radio_2059_init()
171 	b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080);  in b43_radio_2059_init()
173 	b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x0078);  in b43_radio_2059_init()
174 	b43_radio_mask(dev, R2059_XTAL_CONFIG2, ~0x0080);  in b43_radio_2059_init()
177 		b43_radio_2059_rcal(dev);  in b43_radio_2059_init()
178 		b43_radio_2057_rccal(dev);  in b43_radio_2059_init()
181 	b43_radio_mask(dev, R2059_RFPLL_MASTER, ~0x0008);  in b43_radio_2059_init()
188 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)  in b43_phy_ht_force_rf_sequence()  argument
192 	u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);  in b43_phy_ht_force_rf_sequence()
193 	b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);  in b43_phy_ht_force_rf_sequence()
195 	b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);  in b43_phy_ht_force_rf_sequence()
197 		if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {  in b43_phy_ht_force_rf_sequence()
204 		b43err(dev->wl, "Forcing RF sequence timeout\n");  in b43_phy_ht_force_rf_sequence()
206 	b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);  in b43_phy_ht_force_rf_sequence()
209 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)  in b43_phy_ht_pa_override()  argument
211 	struct b43_phy_ht *htphy = dev->phy.ht;  in b43_phy_ht_pa_override()
219 			b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);  in b43_phy_ht_pa_override()
222 			htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);  in b43_phy_ht_pa_override()
225 			b43_phy_write(dev, regs[i], 0x0400);  in b43_phy_ht_pa_override()
233 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)  in b43_phy_ht_classifier()  argument
240 	tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);  in b43_phy_ht_classifier()
244 	b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);  in b43_phy_ht_classifier()
249 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)  in b43_phy_ht_reset_cca()  argument
253 	b43_phy_force_clock(dev, true);  in b43_phy_ht_reset_cca()
254 	bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);  in b43_phy_ht_reset_cca()
255 	b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);  in b43_phy_ht_reset_cca()
257 	b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);  in b43_phy_ht_reset_cca()
258 	b43_phy_force_clock(dev, false);  in b43_phy_ht_reset_cca()
260 	b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);  in b43_phy_ht_reset_cca()
263 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)  in b43_phy_ht_zero_extg()  argument
270 			b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);  in b43_phy_ht_zero_extg()
274 		b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);  in b43_phy_ht_zero_extg()
278 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)  in b43_phy_ht_afe_unk1()  argument
290 		b43_phy_set(dev, ctl_regs[i][1], 0x4);  in b43_phy_ht_afe_unk1()
291 		b43_phy_set(dev, ctl_regs[i][0], 0x4);  in b43_phy_ht_afe_unk1()
292 		b43_phy_mask(dev, ctl_regs[i][1], ~0x1);  in b43_phy_ht_afe_unk1()
293 		b43_phy_set(dev, ctl_regs[i][0], 0x1);  in b43_phy_ht_afe_unk1()
294 		b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);  in b43_phy_ht_afe_unk1()
295 		b43_phy_mask(dev, ctl_regs[i][0], ~0x4);  in b43_phy_ht_afe_unk1()
299 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)  in b43_phy_ht_read_clip_detection()  argument
301 	clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);  in b43_phy_ht_read_clip_detection()
302 	clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);  in b43_phy_ht_read_clip_detection()
303 	clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);  in b43_phy_ht_read_clip_detection()
306 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)  in b43_phy_ht_bphy_init()  argument
313 		b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);  in b43_phy_ht_bphy_init()
318 		b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);  in b43_phy_ht_bphy_init()
321 	b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);  in b43_phy_ht_bphy_init()
324 static void b43_phy_ht_bphy_reset(struct b43_wldev *dev, bool reset)  in b43_phy_ht_bphy_reset()  argument
328 	tmp = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);  in b43_phy_ht_bphy_reset()
329 	b43_write16(dev, B43_MMIO_PSM_PHY_HDR,  in b43_phy_ht_bphy_reset()
334 		b43_phy_set(dev, B43_PHY_B_BBCFG,  in b43_phy_ht_bphy_reset()
337 		b43_phy_mask(dev, B43_PHY_B_BBCFG,  in b43_phy_ht_bphy_reset()
341 	b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp);  in b43_phy_ht_bphy_reset()
348 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)  in b43_phy_ht_stop_playback()  argument
350 	struct b43_phy_ht *phy_ht = dev->phy.ht;  in b43_phy_ht_stop_playback()
354 	tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);  in b43_phy_ht_stop_playback()
356 		b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);  in b43_phy_ht_stop_playback()
358 		b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);  in b43_phy_ht_stop_playback()
360 	b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);  in b43_phy_ht_stop_playback()
364 			b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),  in b43_phy_ht_stop_playback()
366 			b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),  in b43_phy_ht_stop_playback()
372 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)  in b43_phy_ht_load_samples()  argument
377 	b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);  in b43_phy_ht_load_samples()
380 		b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);  in b43_phy_ht_load_samples()
381 		b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);  in b43_phy_ht_load_samples()
387 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,  in b43_phy_ht_run_samples()  argument
390 	struct b43_phy_ht *phy_ht = dev->phy.ht;  in b43_phy_ht_run_samples()
396 			phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));  in b43_phy_ht_run_samples()
399 	b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);  in b43_phy_ht_run_samples()
402 	b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);  in b43_phy_ht_run_samples()
403 	b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);  in b43_phy_ht_run_samples()
405 	save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);  in b43_phy_ht_run_samples()
406 	b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,  in b43_phy_ht_run_samples()
410 	b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);  in b43_phy_ht_run_samples()
411 	b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);  in b43_phy_ht_run_samples()
412 	b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);  in b43_phy_ht_run_samples()
413 	b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);  in b43_phy_ht_run_samples()
416 		if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {  in b43_phy_ht_run_samples()
423 		b43err(dev->wl, "run samples timeout\n");  in b43_phy_ht_run_samples()
425 	b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);  in b43_phy_ht_run_samples()
428 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)  in b43_phy_ht_tx_tone()  argument
432 	samp = b43_phy_ht_load_samples(dev);  in b43_phy_ht_tx_tone()
433 	b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);  in b43_phy_ht_tx_tone()
440 static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,  in b43_phy_ht_rssi_select()  argument
452 		b43err(dev->wl, "RSSI selection for core off not implemented yet\n");  in b43_phy_ht_rssi_select()
463 				b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);  in b43_phy_ht_rssi_select()
464 				b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);  in b43_phy_ht_rssi_select()
465 				b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);  in b43_phy_ht_rssi_select()
466 				b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);  in b43_phy_ht_rssi_select()
468 				b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);  in b43_phy_ht_rssi_select()
469 				b43_radio_write(dev, radio_r[core] | 0x159,  in b43_phy_ht_rssi_select()
473 				b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",  in b43_phy_ht_rssi_select()
480 static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,  in b43_phy_ht_poll_rssi()  argument
496 		phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);  in b43_phy_ht_poll_rssi()
498 	b43_phy_ht_rssi_select(dev, 5, type);  in b43_phy_ht_poll_rssi()
504 		tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);  in b43_phy_ht_poll_rssi()
505 		tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);  in b43_phy_ht_poll_rssi()
506 		tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);  in b43_phy_ht_poll_rssi()
517 		b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);  in b43_phy_ht_poll_rssi()
524 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)  in b43_phy_ht_tx_power_fix()  argument
530 		u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));  in b43_phy_ht_tx_power_fix()
536 		b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);  in b43_phy_ht_tx_power_fix()
538 		b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);  in b43_phy_ht_tx_power_fix()
539 		b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),  in b43_phy_ht_tx_power_fix()
541 		b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),  in b43_phy_ht_tx_power_fix()
546 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)  in b43_phy_ht_tx_power_ctl()  argument
548 	struct b43_phy_ht *phy_ht = dev->phy.ht;  in b43_phy_ht_tx_power_ctl()
561 		if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {  in b43_phy_ht_tx_power_ctl()
565 					b43_phy_read(dev, status_regs[i]);  in b43_phy_ht_tx_power_ctl()
567 		b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);  in b43_phy_ht_tx_power_ctl()
569 		b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);  in b43_phy_ht_tx_power_ctl()
571 		if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {  in b43_phy_ht_tx_power_ctl()
573 				b43_phy_write(dev, cmd_regs[i], 0x32);  in b43_phy_ht_tx_power_ctl()
579 				b43_phy_write(dev, cmd_regs[i],  in b43_phy_ht_tx_power_ctl()
586 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)  in b43_phy_ht_tx_power_ctl_idle_tssi()  argument
588 	struct b43_phy_ht *phy_ht = dev->phy.ht;  in b43_phy_ht_tx_power_ctl_idle_tssi()
595 		save_regs[core][1] = b43_phy_read(dev, base[core] + 6);  in b43_phy_ht_tx_power_ctl_idle_tssi()
596 		save_regs[core][2] = b43_phy_read(dev, base[core] + 7);  in b43_phy_ht_tx_power_ctl_idle_tssi()
597 		save_regs[core][0] = b43_phy_read(dev, base[core] + 0);  in b43_phy_ht_tx_power_ctl_idle_tssi()
599 		b43_phy_write(dev, base[core] + 6, 0);  in b43_phy_ht_tx_power_ctl_idle_tssi()
600 		b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */  in b43_phy_ht_tx_power_ctl_idle_tssi()
601 		b43_phy_set(dev, base[core] + 0, 0x0400);  in b43_phy_ht_tx_power_ctl_idle_tssi()
602 		b43_phy_set(dev, base[core] + 0, 0x1000);  in b43_phy_ht_tx_power_ctl_idle_tssi()
605 	b43_phy_ht_tx_tone(dev);  in b43_phy_ht_tx_power_ctl_idle_tssi()
607 	b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);  in b43_phy_ht_tx_power_ctl_idle_tssi()
608 	b43_phy_ht_stop_playback(dev);  in b43_phy_ht_tx_power_ctl_idle_tssi()
609 	b43_phy_ht_reset_cca(dev);  in b43_phy_ht_tx_power_ctl_idle_tssi()
616 		b43_phy_write(dev, base[core] + 0, save_regs[core][0]);  in b43_phy_ht_tx_power_ctl_idle_tssi()
617 		b43_phy_write(dev, base[core] + 6, save_regs[core][1]);  in b43_phy_ht_tx_power_ctl_idle_tssi()
618 		b43_phy_write(dev, base[core] + 7, save_regs[core][2]);  in b43_phy_ht_tx_power_ctl_idle_tssi()
622 static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)  in b43_phy_ht_tssi_setup()  argument
629 		b43_radio_set(dev, 0x8bf, 0x1);  in b43_phy_ht_tssi_setup()
630 		b43_radio_write(dev, routing[core] | 0x0159, 0x0011);  in b43_phy_ht_tssi_setup()
634 static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)  in b43_phy_ht_tx_power_ctl_setup()  argument
636 	struct b43_phy_ht *phy_ht = dev->phy.ht;  in b43_phy_ht_tx_power_ctl_setup()
637 	struct ssb_sprom *sprom = dev->dev->bus_sprom;  in b43_phy_ht_tx_power_ctl_setup()
643 	u16 freq = dev->phy.chandef->chan->center_freq;  in b43_phy_ht_tx_power_ctl_setup()
646 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {  in b43_phy_ht_tx_power_ctl_setup()
681 	b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);  in b43_phy_ht_tx_power_ctl_setup()
682 	b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,  in b43_phy_ht_tx_power_ctl_setup()
686 	b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);  in b43_phy_ht_tx_power_ctl_setup()
688 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,  in b43_phy_ht_tx_power_ctl_setup()
690 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,  in b43_phy_ht_tx_power_ctl_setup()
692 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,  in b43_phy_ht_tx_power_ctl_setup()
695 	b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,  in b43_phy_ht_tx_power_ctl_setup()
698 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,  in b43_phy_ht_tx_power_ctl_setup()
701 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,  in b43_phy_ht_tx_power_ctl_setup()
704 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,  in b43_phy_ht_tx_power_ctl_setup()
708 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,  in b43_phy_ht_tx_power_ctl_setup()
710 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,  in b43_phy_ht_tx_power_ctl_setup()
714 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)  in b43_phy_ht_tx_power_ctl_setup()
715 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)  in b43_phy_ht_tx_power_ctl_setup()
718 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,  in b43_phy_ht_tx_power_ctl_setup()
721 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,  in b43_phy_ht_tx_power_ctl_setup()
724 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,  in b43_phy_ht_tx_power_ctl_setup()
738 		b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);  in b43_phy_ht_tx_power_ctl_setup()
746 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,  in b43_phy_ht_spur_avoid()  argument
749 	struct bcma_device *core = dev->dev->bdev;  in b43_phy_ht_spur_avoid()
763 	b43_mac_switch_freq(dev, spuravoid);  in b43_phy_ht_spur_avoid()
765 	b43_wireless_core_phy_pll_reset(dev);  in b43_phy_ht_spur_avoid()
768 		b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);  in b43_phy_ht_spur_avoid()
770 		b43_phy_mask(dev, B43_PHY_HT_BBCFG,  in b43_phy_ht_spur_avoid()
773 	b43_phy_ht_reset_cca(dev);  in b43_phy_ht_spur_avoid()
776 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,  in b43_phy_ht_channel_setup()  argument
782 		b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ);  in b43_phy_ht_channel_setup()
784 		b43_phy_ht_bphy_reset(dev, true);  in b43_phy_ht_channel_setup()
787 		b43_phy_set(dev, B43_PHY_HT_BANDCTL, B43_PHY_HT_BANDCTL_5GHZ);  in b43_phy_ht_channel_setup()
790 		b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ);  in b43_phy_ht_channel_setup()
792 		b43_phy_ht_bphy_reset(dev, false);  in b43_phy_ht_channel_setup()
795 	b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);  in b43_phy_ht_channel_setup()
796 	b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);  in b43_phy_ht_channel_setup()
797 	b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);  in b43_phy_ht_channel_setup()
798 	b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);  in b43_phy_ht_channel_setup()
799 	b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);  in b43_phy_ht_channel_setup()
800 	b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);  in b43_phy_ht_channel_setup()
803 		b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);  in b43_phy_ht_channel_setup()
804 		b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);  in b43_phy_ht_channel_setup()
806 		b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,  in b43_phy_ht_channel_setup()
809 			b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);  in b43_phy_ht_channel_setup()
813 		b43_phy_ht_tx_power_fix(dev);  in b43_phy_ht_channel_setup()
815 	b43_phy_ht_spur_avoid(dev, new_channel);  in b43_phy_ht_channel_setup()
817 	b43_phy_write(dev, 0x017e, 0x3830);  in b43_phy_ht_channel_setup()
820 static int b43_phy_ht_set_channel(struct b43_wldev *dev,  in b43_phy_ht_set_channel()  argument
824 	struct b43_phy *phy = &dev->phy;  in b43_phy_ht_set_channel()
829 		chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,  in b43_phy_ht_set_channel()
840 		b43_radio_2059_channel_setup(dev, chent_r2059);  in b43_phy_ht_set_channel()
841 		b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),  in b43_phy_ht_set_channel()
854 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)  in b43_phy_ht_op_allocate()  argument
861 	dev->phy.ht = phy_ht;  in b43_phy_ht_op_allocate()
866 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)  in b43_phy_ht_op_prepare_structs()  argument
868 	struct b43_phy *phy = &dev->phy;  in b43_phy_ht_op_prepare_structs()
882 static int b43_phy_ht_op_init(struct b43_wldev *dev)  in b43_phy_ht_op_init()  argument
884 	struct b43_phy_ht *phy_ht = dev->phy.ht;  in b43_phy_ht_op_init()
889 	if (dev->dev->bus_type != B43_BUS_BCMA) {  in b43_phy_ht_op_init()
890 		b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");  in b43_phy_ht_op_init()
894 	b43_phy_ht_tables_init(dev);  in b43_phy_ht_op_init()
896 	b43_phy_mask(dev, 0x0be, ~0x2);  in b43_phy_ht_op_init()
897 	b43_phy_set(dev, 0x23f, 0x7ff);  in b43_phy_ht_op_init()
898 	b43_phy_set(dev, 0x240, 0x7ff);  in b43_phy_ht_op_init()
899 	b43_phy_set(dev, 0x241, 0x7ff);  in b43_phy_ht_op_init()
901 	b43_phy_ht_zero_extg(dev);  in b43_phy_ht_op_init()
903 	b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);  in b43_phy_ht_op_init()
905 	b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);  in b43_phy_ht_op_init()
906 	b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);  in b43_phy_ht_op_init()
907 	b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);  in b43_phy_ht_op_init()
909 	b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);  in b43_phy_ht_op_init()
910 	b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);  in b43_phy_ht_op_init()
911 	b43_phy_write(dev, 0x20d, 0xb8);  in b43_phy_ht_op_init()
912 	b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);  in b43_phy_ht_op_init()
913 	b43_phy_write(dev, 0x70, 0x50);  in b43_phy_ht_op_init()
914 	b43_phy_write(dev, 0x1ff, 0x30);  in b43_phy_ht_op_init()
919 	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)  in b43_phy_ht_op_init()
920 		b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);  in b43_phy_ht_op_init()
922 		b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,  in b43_phy_ht_op_init()
925 	b43_phy_set(dev, 0xb1, 0x91);  in b43_phy_ht_op_init()
926 	b43_phy_write(dev, 0x32f, 0x0003);  in b43_phy_ht_op_init()
927 	b43_phy_write(dev, 0x077, 0x0010);  in b43_phy_ht_op_init()
928 	b43_phy_write(dev, 0x0b4, 0x0258);  in b43_phy_ht_op_init()
929 	b43_phy_mask(dev, 0x17e, ~0x4000);  in b43_phy_ht_op_init()
931 	b43_phy_write(dev, 0x0b9, 0x0072);  in b43_phy_ht_op_init()
933 	b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);  in b43_phy_ht_op_init()
934 	b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);  in b43_phy_ht_op_init()
935 	b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);  in b43_phy_ht_op_init()
937 	b43_phy_ht_afe_unk1(dev);  in b43_phy_ht_op_init()
939 	b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,  in b43_phy_ht_op_init()
942 	b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);  in b43_phy_ht_op_init()
943 	b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);  in b43_phy_ht_op_init()
945 	b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);  in b43_phy_ht_op_init()
946 	b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);  in b43_phy_ht_op_init()
947 	b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);  in b43_phy_ht_op_init()
949 	b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,  in b43_phy_ht_op_init()
951 	b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,  in b43_phy_ht_op_init()
953 	b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,  in b43_phy_ht_op_init()
956 	b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);  in b43_phy_ht_op_init()
957 	b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);  in b43_phy_ht_op_init()
958 	b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);  in b43_phy_ht_op_init()
960 	b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);  in b43_phy_ht_op_init()
961 	b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);  in b43_phy_ht_op_init()
962 	b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);  in b43_phy_ht_op_init()
963 	b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);  in b43_phy_ht_op_init()
965 	b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,  in b43_phy_ht_op_init()
967 	b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,  in b43_phy_ht_op_init()
970 	b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,  in b43_phy_ht_op_init()
973 	b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);  in b43_phy_ht_op_init()
974 	b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);  in b43_phy_ht_op_init()
975 	b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);  in b43_phy_ht_op_init()
977 	b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);  in b43_phy_ht_op_init()
978 	b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);  in b43_phy_ht_op_init()
979 	b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);  in b43_phy_ht_op_init()
980 	b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);  in b43_phy_ht_op_init()
983 	tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));  in b43_phy_ht_op_init()
984 	b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);  in b43_phy_ht_op_init()
985 	tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));  in b43_phy_ht_op_init()
986 	b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);  in b43_phy_ht_op_init()
987 	tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));  in b43_phy_ht_op_init()
988 	b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);  in b43_phy_ht_op_init()
991 	b43_phy_force_clock(dev, true);  in b43_phy_ht_op_init()
992 	tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);  in b43_phy_ht_op_init()
993 	b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);  in b43_phy_ht_op_init()
994 	b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);  in b43_phy_ht_op_init()
995 	b43_phy_force_clock(dev, false);  in b43_phy_ht_op_init()
997 	b43_mac_phy_clock_set(dev, true);  in b43_phy_ht_op_init()
999 	b43_phy_ht_pa_override(dev, false);  in b43_phy_ht_op_init()
1000 	b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);  in b43_phy_ht_op_init()
1001 	b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);  in b43_phy_ht_op_init()
1002 	b43_phy_ht_pa_override(dev, true);  in b43_phy_ht_op_init()
1005 	b43_phy_ht_classifier(dev, 0, 0);  in b43_phy_ht_op_init()
1006 	b43_phy_ht_read_clip_detection(dev, clip_state);  in b43_phy_ht_op_init()
1008 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)  in b43_phy_ht_op_init()
1009 		b43_phy_ht_bphy_init(dev);  in b43_phy_ht_op_init()
1011 	b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),  in b43_phy_ht_op_init()
1015 	b43_phy_ht_tx_power_fix(dev);  in b43_phy_ht_op_init()
1016 	b43_phy_ht_tx_power_ctl(dev, false);  in b43_phy_ht_op_init()
1017 	b43_phy_ht_tx_power_ctl_idle_tssi(dev);  in b43_phy_ht_op_init()
1018 	b43_phy_ht_tx_power_ctl_setup(dev);  in b43_phy_ht_op_init()
1019 	b43_phy_ht_tssi_setup(dev);  in b43_phy_ht_op_init()
1020 	b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);  in b43_phy_ht_op_init()
1025 static void b43_phy_ht_op_free(struct b43_wldev *dev)  in b43_phy_ht_op_free()  argument
1027 	struct b43_phy *phy = &dev->phy;  in b43_phy_ht_op_free()
1035 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,  in b43_phy_ht_op_software_rfkill()  argument
1038 	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)  in b43_phy_ht_op_software_rfkill()
1039 		b43err(dev->wl, "MAC not suspended\n");  in b43_phy_ht_op_software_rfkill()
1042 		b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD,  in b43_phy_ht_op_software_rfkill()
1045 		if (dev->phy.radio_ver == 0x2059)  in b43_phy_ht_op_software_rfkill()
1046 			b43_radio_2059_init(dev);  in b43_phy_ht_op_software_rfkill()
1050 		b43_switch_channel(dev, dev->phy.channel);  in b43_phy_ht_op_software_rfkill()
1054 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)  in b43_phy_ht_op_switch_analog()  argument
1057 		b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);  in b43_phy_ht_op_switch_analog()
1058 		b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);  in b43_phy_ht_op_switch_analog()
1059 		b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);  in b43_phy_ht_op_switch_analog()
1060 		b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);  in b43_phy_ht_op_switch_analog()
1061 		b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);  in b43_phy_ht_op_switch_analog()
1062 		b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);  in b43_phy_ht_op_switch_analog()
1064 		b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);  in b43_phy_ht_op_switch_analog()
1065 		b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);  in b43_phy_ht_op_switch_analog()
1066 		b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);  in b43_phy_ht_op_switch_analog()
1067 		b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);  in b43_phy_ht_op_switch_analog()
1068 		b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);  in b43_phy_ht_op_switch_analog()
1069 		b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);  in b43_phy_ht_op_switch_analog()
1073 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,  in b43_phy_ht_op_switch_channel()  argument
1076 	struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;  in b43_phy_ht_op_switch_channel()
1078 		cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);  in b43_phy_ht_op_switch_channel()
1080 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {  in b43_phy_ht_op_switch_channel()
1087 	return b43_phy_ht_set_channel(dev, channel, channel_type);  in b43_phy_ht_op_switch_channel()
1090 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)  in b43_phy_ht_op_get_default_chan()  argument
1092 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)  in b43_phy_ht_op_get_default_chan()
1101 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,  in b43_phy_ht_op_maskset()  argument
1104 	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);  in b43_phy_ht_op_maskset()
1105 	b43_write16(dev, B43_MMIO_PHY_DATA,  in b43_phy_ht_op_maskset()
1106 		    (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);  in b43_phy_ht_op_maskset()
1109 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)  in b43_phy_ht_op_radio_read()  argument
1114 	b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);  in b43_phy_ht_op_radio_read()
1115 	return b43_read16(dev, B43_MMIO_RADIO24_DATA);  in b43_phy_ht_op_radio_read()
1118 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,  in b43_phy_ht_op_radio_write()  argument
1121 	b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);  in b43_phy_ht_op_radio_write()
1122 	b43_write16(dev, B43_MMIO_RADIO24_DATA, value);  in b43_phy_ht_op_radio_write()
1126 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)  in b43_phy_ht_op_recalc_txpower()  argument
1131 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)  in b43_phy_ht_op_adjust_txpower()  argument