Lines Matching refs:dev
66 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
80 static void generate_rfatt_list(struct b43_wldev *dev, in generate_rfatt_list() argument
83 struct b43_phy *phy = &dev->phy; in generate_rfatt_list()
123 if (!b43_has_hardware_pctl(dev)) { in generate_rfatt_list()
146 static void generate_bbatt_list(struct b43_wldev *dev, in generate_bbatt_list() argument
167 static void b43_shm_clear_tssi(struct b43_wldev *dev) in b43_shm_clear_tssi() argument
169 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F); in b43_shm_clear_tssi()
170 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F); in b43_shm_clear_tssi()
171 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F); in b43_shm_clear_tssi()
172 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F); in b43_shm_clear_tssi()
176 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel) in b43_synth_pu_workaround() argument
178 struct b43_phy *phy = &dev->phy; in b43_synth_pu_workaround()
188 b43_write16(dev, B43_MMIO_CHANNEL, in b43_synth_pu_workaround()
191 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1)); in b43_synth_pu_workaround()
194 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); in b43_synth_pu_workaround()
198 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev, in b43_gphy_set_baseband_attenuation() argument
201 struct b43_phy *phy = &dev->phy; in b43_gphy_set_baseband_attenuation()
204 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0) in b43_gphy_set_baseband_attenuation()
208 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2)); in b43_gphy_set_baseband_attenuation()
210 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3)); in b43_gphy_set_baseband_attenuation()
215 static void b43_set_txpower_g(struct b43_wldev *dev, in b43_set_txpower_g() argument
219 struct b43_phy *phy = &dev->phy; in b43_set_txpower_g()
239 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_set_txpower_g()
240 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), " in b43_set_txpower_g()
246 b43_gphy_set_baseband_attenuation(dev, bb); in b43_set_txpower_g()
247 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf); in b43_set_txpower_g()
249 b43_radio_write16(dev, 0x43, in b43_set_txpower_g()
252 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F)); in b43_set_txpower_g()
253 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070)); in b43_set_txpower_g()
256 b43_radio_write16(dev, 0x52, tx_magn | tx_bias); in b43_set_txpower_g()
258 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F)); in b43_set_txpower_g()
260 b43_lo_g_adjust(dev); in b43_set_txpower_g()
264 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev) in b43_gphy_tssi_power_lt_init() argument
266 struct b43_phy_g *gphy = dev->phy.g; in b43_gphy_tssi_power_lt_init()
271 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]); in b43_gphy_tssi_power_lt_init()
273 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]); in b43_gphy_tssi_power_lt_init()
277 b43_phy_write(dev, 0x380 + (i / 2), value); in b43_gphy_tssi_power_lt_init()
282 static void b43_gphy_gain_lt_init(struct b43_wldev *dev) in b43_gphy_gain_lt_init() argument
284 struct b43_phy *phy = &dev->phy; in b43_gphy_gain_lt_init()
302 b43_phy_write(dev, 0x3C0 + nr_written, tmp); in b43_gphy_gain_lt_init()
308 static void b43_set_all_gains(struct b43_wldev *dev, in b43_set_all_gains() argument
311 struct b43_phy *phy = &dev->phy; in b43_set_all_gains()
326 b43_ofdmtab_write16(dev, table, i, first); in b43_set_all_gains()
329 b43_ofdmtab_write16(dev, table, i, second); in b43_set_all_gains()
333 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp); in b43_set_all_gains()
334 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp); in b43_set_all_gains()
335 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp); in b43_set_all_gains()
337 b43_dummy_transmission(dev, false, true); in b43_set_all_gains()
340 static void b43_set_original_gains(struct b43_wldev *dev) in b43_set_original_gains() argument
342 struct b43_phy *phy = &dev->phy; in b43_set_original_gains()
360 b43_ofdmtab_write16(dev, table, i, tmp); in b43_set_original_gains()
364 b43_ofdmtab_write16(dev, table, i, i - start); in b43_set_original_gains()
366 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040); in b43_set_original_gains()
367 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040); in b43_set_original_gains()
368 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000); in b43_set_original_gains()
369 b43_dummy_transmission(dev, false, true); in b43_set_original_gains()
373 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val) in b43_nrssi_hw_write() argument
375 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); in b43_nrssi_hw_write()
376 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val); in b43_nrssi_hw_write()
380 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset) in b43_nrssi_hw_read() argument
384 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); in b43_nrssi_hw_read()
385 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA); in b43_nrssi_hw_read()
391 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val) in b43_nrssi_hw_update() argument
397 tmp = b43_nrssi_hw_read(dev, i); in b43_nrssi_hw_update()
400 b43_nrssi_hw_write(dev, i, tmp); in b43_nrssi_hw_update()
405 static void b43_nrssi_mem_update(struct b43_wldev *dev) in b43_nrssi_mem_update() argument
407 struct b43_phy_g *gphy = dev->phy.g; in b43_nrssi_mem_update()
421 static void b43_calc_nrssi_offset(struct b43_wldev *dev) in b43_calc_nrssi_offset() argument
423 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_offset()
429 backup[0] = b43_phy_read(dev, 0x0001); in b43_calc_nrssi_offset()
430 backup[1] = b43_phy_read(dev, 0x0811); in b43_calc_nrssi_offset()
431 backup[2] = b43_phy_read(dev, 0x0812); in b43_calc_nrssi_offset()
433 backup[3] = b43_phy_read(dev, 0x0814); in b43_calc_nrssi_offset()
434 backup[4] = b43_phy_read(dev, 0x0815); in b43_calc_nrssi_offset()
436 backup[5] = b43_phy_read(dev, 0x005A); in b43_calc_nrssi_offset()
437 backup[6] = b43_phy_read(dev, 0x0059); in b43_calc_nrssi_offset()
438 backup[7] = b43_phy_read(dev, 0x0058); in b43_calc_nrssi_offset()
439 backup[8] = b43_phy_read(dev, 0x000A); in b43_calc_nrssi_offset()
440 backup[9] = b43_phy_read(dev, 0x0003); in b43_calc_nrssi_offset()
441 backup[10] = b43_radio_read16(dev, 0x007A); in b43_calc_nrssi_offset()
442 backup[11] = b43_radio_read16(dev, 0x0043); in b43_calc_nrssi_offset()
444 b43_phy_mask(dev, 0x0429, 0x7FFF); in b43_calc_nrssi_offset()
445 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000); in b43_calc_nrssi_offset()
446 b43_phy_set(dev, 0x0811, 0x000C); in b43_calc_nrssi_offset()
447 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004); in b43_calc_nrssi_offset()
448 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2)); in b43_calc_nrssi_offset()
450 backup[12] = b43_phy_read(dev, 0x002E); in b43_calc_nrssi_offset()
451 backup[13] = b43_phy_read(dev, 0x002F); in b43_calc_nrssi_offset()
452 backup[14] = b43_phy_read(dev, 0x080F); in b43_calc_nrssi_offset()
453 backup[15] = b43_phy_read(dev, 0x0810); in b43_calc_nrssi_offset()
454 backup[16] = b43_phy_read(dev, 0x0801); in b43_calc_nrssi_offset()
455 backup[17] = b43_phy_read(dev, 0x0060); in b43_calc_nrssi_offset()
456 backup[18] = b43_phy_read(dev, 0x0014); in b43_calc_nrssi_offset()
457 backup[19] = b43_phy_read(dev, 0x0478); in b43_calc_nrssi_offset()
459 b43_phy_write(dev, 0x002E, 0); in b43_calc_nrssi_offset()
460 b43_phy_write(dev, 0x002F, 0); in b43_calc_nrssi_offset()
461 b43_phy_write(dev, 0x080F, 0); in b43_calc_nrssi_offset()
462 b43_phy_write(dev, 0x0810, 0); in b43_calc_nrssi_offset()
463 b43_phy_set(dev, 0x0478, 0x0100); in b43_calc_nrssi_offset()
464 b43_phy_set(dev, 0x0801, 0x0040); in b43_calc_nrssi_offset()
465 b43_phy_set(dev, 0x0060, 0x0040); in b43_calc_nrssi_offset()
466 b43_phy_set(dev, 0x0014, 0x0200); in b43_calc_nrssi_offset()
468 b43_radio_set(dev, 0x007A, 0x0070); in b43_calc_nrssi_offset()
469 b43_radio_set(dev, 0x007A, 0x0080); in b43_calc_nrssi_offset()
472 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
477 b43_radio_write16(dev, 0x007B, i); in b43_calc_nrssi_offset()
480 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
489 b43_radio_mask(dev, 0x007A, 0x007F); in b43_calc_nrssi_offset()
491 b43_phy_set(dev, 0x0814, 0x0001); in b43_calc_nrssi_offset()
492 b43_phy_mask(dev, 0x0815, 0xFFFE); in b43_calc_nrssi_offset()
494 b43_phy_set(dev, 0x0811, 0x000C); in b43_calc_nrssi_offset()
495 b43_phy_set(dev, 0x0812, 0x000C); in b43_calc_nrssi_offset()
496 b43_phy_set(dev, 0x0811, 0x0030); in b43_calc_nrssi_offset()
497 b43_phy_set(dev, 0x0812, 0x0030); in b43_calc_nrssi_offset()
498 b43_phy_write(dev, 0x005A, 0x0480); in b43_calc_nrssi_offset()
499 b43_phy_write(dev, 0x0059, 0x0810); in b43_calc_nrssi_offset()
500 b43_phy_write(dev, 0x0058, 0x000D); in b43_calc_nrssi_offset()
502 b43_phy_write(dev, 0x0003, 0x0122); in b43_calc_nrssi_offset()
504 b43_phy_set(dev, 0x000A, 0x2000); in b43_calc_nrssi_offset()
507 b43_phy_set(dev, 0x0814, 0x0004); in b43_calc_nrssi_offset()
508 b43_phy_mask(dev, 0x0815, 0xFFFB); in b43_calc_nrssi_offset()
510 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); in b43_calc_nrssi_offset()
511 b43_radio_set(dev, 0x007A, 0x000F); in b43_calc_nrssi_offset()
512 b43_set_all_gains(dev, 3, 0, 1); in b43_calc_nrssi_offset()
513 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F); in b43_calc_nrssi_offset()
515 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
520 b43_radio_write16(dev, 0x007B, i); in b43_calc_nrssi_offset()
523 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & in b43_calc_nrssi_offset()
535 b43_radio_write16(dev, 0x007B, saved); in b43_calc_nrssi_offset()
538 b43_phy_write(dev, 0x002E, backup[12]); in b43_calc_nrssi_offset()
539 b43_phy_write(dev, 0x002F, backup[13]); in b43_calc_nrssi_offset()
540 b43_phy_write(dev, 0x080F, backup[14]); in b43_calc_nrssi_offset()
541 b43_phy_write(dev, 0x0810, backup[15]); in b43_calc_nrssi_offset()
544 b43_phy_write(dev, 0x0814, backup[3]); in b43_calc_nrssi_offset()
545 b43_phy_write(dev, 0x0815, backup[4]); in b43_calc_nrssi_offset()
547 b43_phy_write(dev, 0x005A, backup[5]); in b43_calc_nrssi_offset()
548 b43_phy_write(dev, 0x0059, backup[6]); in b43_calc_nrssi_offset()
549 b43_phy_write(dev, 0x0058, backup[7]); in b43_calc_nrssi_offset()
550 b43_phy_write(dev, 0x000A, backup[8]); in b43_calc_nrssi_offset()
551 b43_phy_write(dev, 0x0003, backup[9]); in b43_calc_nrssi_offset()
552 b43_radio_write16(dev, 0x0043, backup[11]); in b43_calc_nrssi_offset()
553 b43_radio_write16(dev, 0x007A, backup[10]); in b43_calc_nrssi_offset()
554 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2); in b43_calc_nrssi_offset()
555 b43_phy_set(dev, 0x0429, 0x8000); in b43_calc_nrssi_offset()
556 b43_set_original_gains(dev); in b43_calc_nrssi_offset()
558 b43_phy_write(dev, 0x0801, backup[16]); in b43_calc_nrssi_offset()
559 b43_phy_write(dev, 0x0060, backup[17]); in b43_calc_nrssi_offset()
560 b43_phy_write(dev, 0x0014, backup[18]); in b43_calc_nrssi_offset()
561 b43_phy_write(dev, 0x0478, backup[19]); in b43_calc_nrssi_offset()
563 b43_phy_write(dev, 0x0001, backup[0]); in b43_calc_nrssi_offset()
564 b43_phy_write(dev, 0x0812, backup[2]); in b43_calc_nrssi_offset()
565 b43_phy_write(dev, 0x0811, backup[1]); in b43_calc_nrssi_offset()
568 static void b43_calc_nrssi_slope(struct b43_wldev *dev) in b43_calc_nrssi_slope() argument
570 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_slope()
581 b43_calc_nrssi_offset(dev); in b43_calc_nrssi_slope()
583 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); in b43_calc_nrssi_slope()
584 b43_phy_mask(dev, 0x0802, 0xFFFC); in b43_calc_nrssi_slope()
585 backup[7] = b43_read16(dev, 0x03E2); in b43_calc_nrssi_slope()
586 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000); in b43_calc_nrssi_slope()
587 backup[0] = b43_radio_read16(dev, 0x007A); in b43_calc_nrssi_slope()
588 backup[1] = b43_radio_read16(dev, 0x0052); in b43_calc_nrssi_slope()
589 backup[2] = b43_radio_read16(dev, 0x0043); in b43_calc_nrssi_slope()
590 backup[3] = b43_phy_read(dev, 0x0015); in b43_calc_nrssi_slope()
591 backup[4] = b43_phy_read(dev, 0x005A); in b43_calc_nrssi_slope()
592 backup[5] = b43_phy_read(dev, 0x0059); in b43_calc_nrssi_slope()
593 backup[6] = b43_phy_read(dev, 0x0058); in b43_calc_nrssi_slope()
594 backup[8] = b43_read16(dev, 0x03E6); in b43_calc_nrssi_slope()
595 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT); in b43_calc_nrssi_slope()
597 backup[10] = b43_phy_read(dev, 0x002E); in b43_calc_nrssi_slope()
598 backup[11] = b43_phy_read(dev, 0x002F); in b43_calc_nrssi_slope()
599 backup[12] = b43_phy_read(dev, 0x080F); in b43_calc_nrssi_slope()
600 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL); in b43_calc_nrssi_slope()
601 backup[14] = b43_phy_read(dev, 0x0801); in b43_calc_nrssi_slope()
602 backup[15] = b43_phy_read(dev, 0x0060); in b43_calc_nrssi_slope()
603 backup[16] = b43_phy_read(dev, 0x0014); in b43_calc_nrssi_slope()
604 backup[17] = b43_phy_read(dev, 0x0478); in b43_calc_nrssi_slope()
605 b43_phy_write(dev, 0x002E, 0); in b43_calc_nrssi_slope()
606 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0); in b43_calc_nrssi_slope()
611 b43_phy_set(dev, 0x0478, 0x0100); in b43_calc_nrssi_slope()
612 b43_phy_set(dev, 0x0801, 0x0040); in b43_calc_nrssi_slope()
616 b43_phy_mask(dev, 0x0801, 0xFFBF); in b43_calc_nrssi_slope()
619 b43_phy_set(dev, 0x0060, 0x0040); in b43_calc_nrssi_slope()
620 b43_phy_set(dev, 0x0014, 0x0200); in b43_calc_nrssi_slope()
622 b43_radio_set(dev, 0x007A, 0x0070); in b43_calc_nrssi_slope()
623 b43_set_all_gains(dev, 0, 8, 0); in b43_calc_nrssi_slope()
624 b43_radio_mask(dev, 0x007A, 0x00F7); in b43_calc_nrssi_slope()
626 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030); in b43_calc_nrssi_slope()
627 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010); in b43_calc_nrssi_slope()
629 b43_radio_set(dev, 0x007A, 0x0080); in b43_calc_nrssi_slope()
632 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_slope()
636 b43_radio_mask(dev, 0x007A, 0x007F); in b43_calc_nrssi_slope()
638 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); in b43_calc_nrssi_slope()
641 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_calc_nrssi_slope()
642 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_calc_nrssi_slope()
644 b43_radio_set(dev, 0x007A, 0x000F); in b43_calc_nrssi_slope()
645 b43_phy_write(dev, 0x0015, 0xF330); in b43_calc_nrssi_slope()
647 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020); in b43_calc_nrssi_slope()
648 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020); in b43_calc_nrssi_slope()
651 b43_set_all_gains(dev, 3, 0, 1); in b43_calc_nrssi_slope()
653 b43_radio_write16(dev, 0x0043, 0x001F); in b43_calc_nrssi_slope()
655 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F; in b43_calc_nrssi_slope()
656 b43_radio_write16(dev, 0x0052, tmp | 0x0060); in b43_calc_nrssi_slope()
657 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0; in b43_calc_nrssi_slope()
658 b43_radio_write16(dev, 0x0043, tmp | 0x0009); in b43_calc_nrssi_slope()
660 b43_phy_write(dev, 0x005A, 0x0480); in b43_calc_nrssi_slope()
661 b43_phy_write(dev, 0x0059, 0x0810); in b43_calc_nrssi_slope()
662 b43_phy_write(dev, 0x0058, 0x000D); in b43_calc_nrssi_slope()
664 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_slope()
676 b43_phy_write(dev, 0x002E, backup[10]); in b43_calc_nrssi_slope()
677 b43_phy_write(dev, 0x002F, backup[11]); in b43_calc_nrssi_slope()
678 b43_phy_write(dev, 0x080F, backup[12]); in b43_calc_nrssi_slope()
679 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]); in b43_calc_nrssi_slope()
682 b43_phy_mask(dev, 0x0812, 0xFFCF); in b43_calc_nrssi_slope()
683 b43_phy_mask(dev, 0x0811, 0xFFCF); in b43_calc_nrssi_slope()
686 b43_radio_write16(dev, 0x007A, backup[0]); in b43_calc_nrssi_slope()
687 b43_radio_write16(dev, 0x0052, backup[1]); in b43_calc_nrssi_slope()
688 b43_radio_write16(dev, 0x0043, backup[2]); in b43_calc_nrssi_slope()
689 b43_write16(dev, 0x03E2, backup[7]); in b43_calc_nrssi_slope()
690 b43_write16(dev, 0x03E6, backup[8]); in b43_calc_nrssi_slope()
691 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]); in b43_calc_nrssi_slope()
692 b43_phy_write(dev, 0x0015, backup[3]); in b43_calc_nrssi_slope()
693 b43_phy_write(dev, 0x005A, backup[4]); in b43_calc_nrssi_slope()
694 b43_phy_write(dev, 0x0059, backup[5]); in b43_calc_nrssi_slope()
695 b43_phy_write(dev, 0x0058, backup[6]); in b43_calc_nrssi_slope()
696 b43_synth_pu_workaround(dev, phy->channel); in b43_calc_nrssi_slope()
697 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002)); in b43_calc_nrssi_slope()
698 b43_set_original_gains(dev); in b43_calc_nrssi_slope()
699 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); in b43_calc_nrssi_slope()
701 b43_phy_write(dev, 0x0801, backup[14]); in b43_calc_nrssi_slope()
702 b43_phy_write(dev, 0x0060, backup[15]); in b43_calc_nrssi_slope()
703 b43_phy_write(dev, 0x0014, backup[16]); in b43_calc_nrssi_slope()
704 b43_phy_write(dev, 0x0478, backup[17]); in b43_calc_nrssi_slope()
706 b43_nrssi_mem_update(dev); in b43_calc_nrssi_slope()
707 b43_calc_nrssi_threshold(dev); in b43_calc_nrssi_slope()
710 static void b43_calc_nrssi_threshold(struct b43_wldev *dev) in b43_calc_nrssi_threshold() argument
712 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_threshold()
721 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { in b43_calc_nrssi_threshold()
722 tmp16 = b43_nrssi_hw_read(dev, 0x20); in b43_calc_nrssi_threshold()
726 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB); in b43_calc_nrssi_threshold()
728 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED); in b43_calc_nrssi_threshold()
760 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000; in b43_calc_nrssi_threshold()
763 b43_phy_write(dev, 0x048A, tmp_u16); in b43_calc_nrssi_threshold()
806 b43_phy_read(dev, (offset))); \
810 b43_phy_write(dev, (offset), \
817 b43_radio_read16(dev, (offset))); \
821 b43_radio_write16(dev, (offset), \
828 b43_ofdmtab_read16(dev, (table), (offset))); \
832 b43_ofdmtab_write16(dev, (table), (offset), \
838 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode) in b43_radio_interference_mitigation_enable() argument
840 struct b43_phy *phy = &dev->phy; in b43_radio_interference_mitigation_enable()
849 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
850 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000); in b43_radio_interference_mitigation_enable()
854 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E); in b43_radio_interference_mitigation_enable()
862 b43_radio_write16(dev, 0x0078, flipped); in b43_radio_interference_mitigation_enable()
864 b43_calc_nrssi_threshold(dev); in b43_radio_interference_mitigation_enable()
867 b43_phy_write(dev, 0x0406, 0x7E28); in b43_radio_interference_mitigation_enable()
869 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
870 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000); in b43_radio_interference_mitigation_enable()
873 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008); in b43_radio_interference_mitigation_enable()
875 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605); in b43_radio_interference_mitigation_enable()
877 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204); in b43_radio_interference_mitigation_enable()
879 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803); in b43_radio_interference_mitigation_enable()
881 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605); in b43_radio_interference_mitigation_enable()
884 b43_phy_write(dev, 0x04A7, 0x0002); in b43_radio_interference_mitigation_enable()
886 b43_phy_write(dev, 0x04A3, 0x287A); in b43_radio_interference_mitigation_enable()
888 b43_phy_write(dev, 0x04A9, 0x2027); in b43_radio_interference_mitigation_enable()
890 b43_phy_write(dev, 0x0493, 0x32F5); in b43_radio_interference_mitigation_enable()
892 b43_phy_write(dev, 0x04AA, 0x2027); in b43_radio_interference_mitigation_enable()
894 b43_phy_write(dev, 0x04AC, 0x32F5); in b43_radio_interference_mitigation_enable()
897 if (b43_phy_read(dev, 0x0033) & 0x0800) in b43_radio_interference_mitigation_enable()
937 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000); in b43_radio_interference_mitigation_enable()
938 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002); in b43_radio_interference_mitigation_enable()
940 b43_phy_write(dev, 0x0033, 0x0800); in b43_radio_interference_mitigation_enable()
941 b43_phy_write(dev, 0x04A3, 0x2027); in b43_radio_interference_mitigation_enable()
942 b43_phy_write(dev, 0x04A9, 0x1CA8); in b43_radio_interference_mitigation_enable()
943 b43_phy_write(dev, 0x0493, 0x287A); in b43_radio_interference_mitigation_enable()
944 b43_phy_write(dev, 0x04AA, 0x1CA8); in b43_radio_interference_mitigation_enable()
945 b43_phy_write(dev, 0x04AC, 0x287A); in b43_radio_interference_mitigation_enable()
947 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A); in b43_radio_interference_mitigation_enable()
948 b43_phy_write(dev, 0x04A7, 0x000D); in b43_radio_interference_mitigation_enable()
951 b43_phy_write(dev, 0x0406, 0xFF0D); in b43_radio_interference_mitigation_enable()
953 b43_phy_write(dev, 0x04C0, 0xFFFF); in b43_radio_interference_mitigation_enable()
954 b43_phy_write(dev, 0x04C1, 0x00A9); in b43_radio_interference_mitigation_enable()
956 b43_phy_write(dev, 0x04C0, 0x00C1); in b43_radio_interference_mitigation_enable()
957 b43_phy_write(dev, 0x04C1, 0x0059); in b43_radio_interference_mitigation_enable()
960 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800); in b43_radio_interference_mitigation_enable()
961 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015); in b43_radio_interference_mitigation_enable()
962 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000); in b43_radio_interference_mitigation_enable()
963 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00); in b43_radio_interference_mitigation_enable()
964 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000); in b43_radio_interference_mitigation_enable()
965 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800); in b43_radio_interference_mitigation_enable()
966 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010); in b43_radio_interference_mitigation_enable()
967 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005); in b43_radio_interference_mitigation_enable()
968 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010); in b43_radio_interference_mitigation_enable()
969 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006); in b43_radio_interference_mitigation_enable()
970 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800); in b43_radio_interference_mitigation_enable()
971 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500); in b43_radio_interference_mitigation_enable()
972 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B); in b43_radio_interference_mitigation_enable()
975 b43_phy_mask(dev, 0x048A, 0x7FFF); in b43_radio_interference_mitigation_enable()
976 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8); in b43_radio_interference_mitigation_enable()
977 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8); in b43_radio_interference_mitigation_enable()
978 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D); in b43_radio_interference_mitigation_enable()
980 b43_phy_set(dev, 0x048A, 0x1000); in b43_radio_interference_mitigation_enable()
981 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000); in b43_radio_interference_mitigation_enable()
982 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW); in b43_radio_interference_mitigation_enable()
985 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
987 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200); in b43_radio_interference_mitigation_enable()
989 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F); in b43_radio_interference_mitigation_enable()
990 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300); in b43_radio_interference_mitigation_enable()
992 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); in b43_radio_interference_mitigation_enable()
993 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); in b43_radio_interference_mitigation_enable()
994 b43_phy_mask(dev, 0x04AD, 0x00FF); in b43_radio_interference_mitigation_enable()
996 b43_calc_nrssi_slope(dev); in b43_radio_interference_mitigation_enable()
1004 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode) in b43_radio_interference_mitigation_disable() argument
1006 struct b43_phy *phy = &dev->phy; in b43_radio_interference_mitigation_disable()
1013 b43_phy_mask(dev, 0x042B, ~0x0800); in b43_radio_interference_mitigation_disable()
1014 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); in b43_radio_interference_mitigation_disable()
1018 b43_calc_nrssi_threshold(dev); in b43_radio_interference_mitigation_disable()
1020 b43_phy_mask(dev, 0x042B, ~0x0800); in b43_radio_interference_mitigation_disable()
1021 if (!dev->bad_frames_preempt) { in b43_radio_interference_mitigation_disable()
1022 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11)); in b43_radio_interference_mitigation_disable()
1024 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); in b43_radio_interference_mitigation_disable()
1038 if (!(b43_phy_read(dev, 0x0033) & 0x0800)) in b43_radio_interference_mitigation_disable()
1076 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW); in b43_radio_interference_mitigation_disable()
1077 b43_calc_nrssi_slope(dev); in b43_radio_interference_mitigation_disable()
1091 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev) in b43_radio_core_calibration_value() argument
1102 reg = b43_radio_read16(dev, 0x60); in b43_radio_core_calibration_value()
1112 static u16 radio2050_rfover_val(struct b43_wldev *dev, in radio2050_rfover_val() argument
1115 struct b43_phy *phy = &dev->phy; in radio2050_rfover_val()
1117 struct ssb_sprom *sprom = dev->dev->bus_sprom; in radio2050_rfover_val()
1257 static u16 b43_radio_init2050(struct b43_wldev *dev) in b43_radio_init2050() argument
1259 struct b43_phy *phy = &dev->phy; in b43_radio_init2050()
1269 sav.radio_43 = b43_radio_read16(dev, 0x43); in b43_radio_init2050()
1270 sav.radio_51 = b43_radio_read16(dev, 0x51); in b43_radio_init2050()
1271 sav.radio_52 = b43_radio_read16(dev, 0x52); in b43_radio_init2050()
1272 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); in b43_radio_init2050()
1273 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A)); in b43_radio_init2050()
1274 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59)); in b43_radio_init2050()
1275 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58)); in b43_radio_init2050()
1278 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); in b43_radio_init2050()
1279 sav.reg_3EC = b43_read16(dev, 0x3EC); in b43_radio_init2050()
1281 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF); in b43_radio_init2050()
1282 b43_write16(dev, 0x3EC, 0x3F3F); in b43_radio_init2050()
1284 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); in b43_radio_init2050()
1285 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_radio_init2050()
1286 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); in b43_radio_init2050()
1288 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); in b43_radio_init2050()
1289 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); in b43_radio_init2050()
1290 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); in b43_radio_init2050()
1292 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); in b43_radio_init2050()
1293 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC); in b43_radio_init2050()
1294 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF); in b43_radio_init2050()
1295 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC); in b43_radio_init2050()
1297 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); in b43_radio_init2050()
1298 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL); in b43_radio_init2050()
1301 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); in b43_radio_init2050()
1303 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); in b43_radio_init2050()
1304 b43_phy_write(dev, B43_PHY_LO_CTL, 0); in b43_radio_init2050()
1307 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1308 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1310 b43_phy_write(dev, B43_PHY_RFOVER, in b43_radio_init2050()
1311 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0)); in b43_radio_init2050()
1313 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000); in b43_radio_init2050()
1315 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); in b43_radio_init2050()
1316 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F); in b43_radio_init2050()
1317 sav.reg_3E6 = b43_read16(dev, 0x3E6); in b43_radio_init2050()
1318 sav.reg_3F4 = b43_read16(dev, 0x3F4); in b43_radio_init2050()
1321 b43_write16(dev, 0x03E6, 0x0122); in b43_radio_init2050()
1324 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40); in b43_radio_init2050()
1326 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_radio_init2050()
1327 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000)); in b43_radio_init2050()
1330 rcc = b43_radio_core_calibration_value(dev); in b43_radio_init2050()
1333 b43_radio_write16(dev, 0x78, 0x26); in b43_radio_init2050()
1335 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1336 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1339 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF); in b43_radio_init2050()
1340 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403); in b43_radio_init2050()
1342 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1343 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1346 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0); in b43_radio_init2050()
1347 b43_radio_set(dev, 0x51, 0x0004); in b43_radio_init2050()
1349 b43_radio_write16(dev, 0x43, 0x1F); in b43_radio_init2050()
1351 b43_radio_write16(dev, 0x52, 0); in b43_radio_init2050()
1352 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009); in b43_radio_init2050()
1354 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1357 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480); in b43_radio_init2050()
1358 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_radio_init2050()
1359 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_radio_init2050()
1361 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1362 radio2050_rfover_val(dev, in b43_radio_init2050()
1366 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1369 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1370 radio2050_rfover_val(dev, in b43_radio_init2050()
1374 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); in b43_radio_init2050()
1377 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1378 radio2050_rfover_val(dev, in b43_radio_init2050()
1382 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); in b43_radio_init2050()
1384 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_radio_init2050()
1385 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1387 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1388 radio2050_rfover_val(dev, in b43_radio_init2050()
1392 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1396 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1402 b43_radio_write16(dev, 0x78, radio78); in b43_radio_init2050()
1405 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80); in b43_radio_init2050()
1406 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_radio_init2050()
1407 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_radio_init2050()
1409 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1410 radio2050_rfover_val(dev, in b43_radio_init2050()
1415 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1418 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1419 radio2050_rfover_val(dev, in b43_radio_init2050()
1424 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); in b43_radio_init2050()
1427 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1428 radio2050_rfover_val(dev, in b43_radio_init2050()
1433 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); in b43_radio_init2050()
1435 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_radio_init2050()
1436 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1438 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1439 radio2050_rfover_val(dev, in b43_radio_init2050()
1444 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1453 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl); in b43_radio_init2050()
1454 b43_radio_write16(dev, 0x51, sav.radio_51); in b43_radio_init2050()
1455 b43_radio_write16(dev, 0x52, sav.radio_52); in b43_radio_init2050()
1456 b43_radio_write16(dev, 0x43, sav.radio_43); in b43_radio_init2050()
1457 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A); in b43_radio_init2050()
1458 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59); in b43_radio_init2050()
1459 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58); in b43_radio_init2050()
1460 b43_write16(dev, 0x3E6, sav.reg_3E6); in b43_radio_init2050()
1462 b43_write16(dev, 0x3F4, sav.reg_3F4); in b43_radio_init2050()
1463 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl); in b43_radio_init2050()
1464 b43_synth_pu_workaround(dev, phy->channel); in b43_radio_init2050()
1466 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30); in b43_radio_init2050()
1467 b43_write16(dev, 0x3EC, sav.reg_3EC); in b43_radio_init2050()
1469 b43_write16(dev, B43_MMIO_PHY_RADIO, in b43_radio_init2050()
1470 b43_read16(dev, B43_MMIO_PHY_RADIO) in b43_radio_init2050()
1472 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover); in b43_radio_init2050()
1473 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval); in b43_radio_init2050()
1474 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover); in b43_radio_init2050()
1475 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, in b43_radio_init2050()
1477 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0); in b43_radio_init2050()
1478 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl); in b43_radio_init2050()
1480 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask); in b43_radio_init2050()
1481 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl); in b43_radio_init2050()
1492 static void b43_phy_initb5(struct b43_wldev *dev) in b43_phy_initb5() argument
1494 struct b43_phy *phy = &dev->phy; in b43_phy_initb5()
1500 b43_radio_set(dev, 0x007A, 0x0050); in b43_phy_initb5()
1502 if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) && in b43_phy_initb5()
1503 (dev->dev->board_type != SSB_BOARD_BU4306)) { in b43_phy_initb5()
1506 b43_phy_write(dev, offset, value); in b43_phy_initb5()
1510 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700); in b43_phy_initb5()
1512 b43_phy_write(dev, 0x0038, 0x0667); in b43_phy_initb5()
1516 b43_radio_set(dev, 0x007A, 0x0020); in b43_phy_initb5()
1517 b43_radio_set(dev, 0x0051, 0x0004); in b43_phy_initb5()
1519 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000); in b43_phy_initb5()
1521 b43_phy_set(dev, 0x0802, 0x0100); in b43_phy_initb5()
1522 b43_phy_set(dev, 0x042B, 0x2000); in b43_phy_initb5()
1524 b43_phy_write(dev, 0x001C, 0x186A); in b43_phy_initb5()
1526 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900); in b43_phy_initb5()
1527 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064); in b43_phy_initb5()
1528 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A); in b43_phy_initb5()
1531 if (dev->bad_frames_preempt) { in b43_phy_initb5()
1532 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11)); in b43_phy_initb5()
1536 b43_phy_write(dev, 0x0026, 0xCE00); in b43_phy_initb5()
1537 b43_phy_write(dev, 0x0021, 0x3763); in b43_phy_initb5()
1538 b43_phy_write(dev, 0x0022, 0x1BC3); in b43_phy_initb5()
1539 b43_phy_write(dev, 0x0023, 0x06F9); in b43_phy_initb5()
1540 b43_phy_write(dev, 0x0024, 0x037E); in b43_phy_initb5()
1542 b43_phy_write(dev, 0x0026, 0xCC00); in b43_phy_initb5()
1543 b43_phy_write(dev, 0x0030, 0x00C6); in b43_phy_initb5()
1544 b43_write16(dev, 0x03EC, 0x3F22); in b43_phy_initb5()
1547 b43_phy_write(dev, 0x0020, 0x3E1C); in b43_phy_initb5()
1549 b43_phy_write(dev, 0x0020, 0x301C); in b43_phy_initb5()
1552 b43_write16(dev, 0x03E4, 0x3000); in b43_phy_initb5()
1556 b43_gphy_channel_switch(dev, 7, 0); in b43_phy_initb5()
1559 b43_radio_write16(dev, 0x0075, 0x0080); in b43_phy_initb5()
1560 b43_radio_write16(dev, 0x0079, 0x0081); in b43_phy_initb5()
1563 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb5()
1564 b43_radio_write16(dev, 0x0050, 0x0023); in b43_phy_initb5()
1567 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb5()
1568 b43_radio_write16(dev, 0x005A, 0x0070); in b43_phy_initb5()
1571 b43_radio_write16(dev, 0x005B, 0x007B); in b43_phy_initb5()
1572 b43_radio_write16(dev, 0x005C, 0x00B0); in b43_phy_initb5()
1574 b43_radio_set(dev, 0x007A, 0x0007); in b43_phy_initb5()
1576 b43_gphy_channel_switch(dev, old_channel, 0); in b43_phy_initb5()
1578 b43_phy_write(dev, 0x0014, 0x0080); in b43_phy_initb5()
1579 b43_phy_write(dev, 0x0032, 0x00CA); in b43_phy_initb5()
1580 b43_phy_write(dev, 0x002A, 0x88A3); in b43_phy_initb5()
1582 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); in b43_phy_initb5()
1585 b43_radio_write16(dev, 0x005D, 0x000D); in b43_phy_initb5()
1587 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004); in b43_phy_initb5()
1591 static void b43_phy_initb6(struct b43_wldev *dev) in b43_phy_initb6() argument
1593 struct b43_phy *phy = &dev->phy; in b43_phy_initb6()
1598 b43_phy_write(dev, 0x003E, 0x817A); in b43_phy_initb6()
1599 b43_radio_write16(dev, 0x007A, in b43_phy_initb6()
1600 (b43_radio_read16(dev, 0x007A) | 0x0058)); in b43_phy_initb6()
1602 b43_radio_write16(dev, 0x51, 0x37); in b43_phy_initb6()
1603 b43_radio_write16(dev, 0x52, 0x70); in b43_phy_initb6()
1604 b43_radio_write16(dev, 0x53, 0xB3); in b43_phy_initb6()
1605 b43_radio_write16(dev, 0x54, 0x9B); in b43_phy_initb6()
1606 b43_radio_write16(dev, 0x5A, 0x88); in b43_phy_initb6()
1607 b43_radio_write16(dev, 0x5B, 0x88); in b43_phy_initb6()
1608 b43_radio_write16(dev, 0x5D, 0x88); in b43_phy_initb6()
1609 b43_radio_write16(dev, 0x5E, 0x88); in b43_phy_initb6()
1610 b43_radio_write16(dev, 0x7D, 0x88); in b43_phy_initb6()
1611 b43_hf_write(dev, b43_hf_read(dev) in b43_phy_initb6()
1616 b43_radio_write16(dev, 0x51, 0); in b43_phy_initb6()
1617 b43_radio_write16(dev, 0x52, 0x40); in b43_phy_initb6()
1618 b43_radio_write16(dev, 0x53, 0xB7); in b43_phy_initb6()
1619 b43_radio_write16(dev, 0x54, 0x98); in b43_phy_initb6()
1620 b43_radio_write16(dev, 0x5A, 0x88); in b43_phy_initb6()
1621 b43_radio_write16(dev, 0x5B, 0x6B); in b43_phy_initb6()
1622 b43_radio_write16(dev, 0x5C, 0x0F); in b43_phy_initb6()
1623 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) { in b43_phy_initb6()
1624 b43_radio_write16(dev, 0x5D, 0xFA); in b43_phy_initb6()
1625 b43_radio_write16(dev, 0x5E, 0xD8); in b43_phy_initb6()
1627 b43_radio_write16(dev, 0x5D, 0xF5); in b43_phy_initb6()
1628 b43_radio_write16(dev, 0x5E, 0xB8); in b43_phy_initb6()
1630 b43_radio_write16(dev, 0x0073, 0x0003); in b43_phy_initb6()
1631 b43_radio_write16(dev, 0x007D, 0x00A8); in b43_phy_initb6()
1632 b43_radio_write16(dev, 0x007C, 0x0001); in b43_phy_initb6()
1633 b43_radio_write16(dev, 0x007E, 0x0008); in b43_phy_initb6()
1637 b43_phy_write(dev, offset, val); in b43_phy_initb6()
1642 b43_phy_write(dev, offset, val); in b43_phy_initb6()
1647 b43_phy_write(dev, offset, (val & 0x3F3F)); in b43_phy_initb6()
1651 b43_radio_set(dev, 0x007A, 0x0020); in b43_phy_initb6()
1652 b43_radio_set(dev, 0x0051, 0x0004); in b43_phy_initb6()
1653 b43_phy_set(dev, 0x0802, 0x0100); in b43_phy_initb6()
1654 b43_phy_set(dev, 0x042B, 0x2000); in b43_phy_initb6()
1655 b43_phy_write(dev, 0x5B, 0); in b43_phy_initb6()
1656 b43_phy_write(dev, 0x5C, 0); in b43_phy_initb6()
1661 b43_gphy_channel_switch(dev, 1, 0); in b43_phy_initb6()
1663 b43_gphy_channel_switch(dev, 13, 0); in b43_phy_initb6()
1665 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb6()
1666 b43_radio_write16(dev, 0x0050, 0x0023); in b43_phy_initb6()
1669 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C) in b43_phy_initb6()
1671 b43_radio_write16(dev, 0x50, 0x20); in b43_phy_initb6()
1674 b43_radio_write16(dev, 0x50, 0x20); in b43_phy_initb6()
1675 b43_radio_write16(dev, 0x5A, 0x70); in b43_phy_initb6()
1676 b43_radio_write16(dev, 0x5B, 0x7B); in b43_phy_initb6()
1677 b43_radio_write16(dev, 0x5C, 0xB0); in b43_phy_initb6()
1679 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007); in b43_phy_initb6()
1681 b43_gphy_channel_switch(dev, old_channel, 0); in b43_phy_initb6()
1683 b43_phy_write(dev, 0x0014, 0x0200); in b43_phy_initb6()
1685 b43_phy_write(dev, 0x2A, 0x88C2); in b43_phy_initb6()
1687 b43_phy_write(dev, 0x2A, 0x8AC0); in b43_phy_initb6()
1688 b43_phy_write(dev, 0x0038, 0x0668); in b43_phy_initb6()
1689 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); in b43_phy_initb6()
1691 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003); in b43_phy_initb6()
1693 b43_radio_write16(dev, 0x005D, 0x000D); in b43_phy_initb6()
1696 b43_write16(dev, 0x3E4, 9); in b43_phy_initb6()
1697 b43_phy_mask(dev, 0x61, 0x0FFF); in b43_phy_initb6()
1699 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004); in b43_phy_initb6()
1704 b43_write16(dev, 0x03E6, 0x0); in b43_phy_initb6()
1707 static void b43_calc_loopback_gain(struct b43_wldev *dev) in b43_calc_loopback_gain() argument
1709 struct b43_phy *phy = &dev->phy; in b43_calc_loopback_gain()
1718 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0); in b43_calc_loopback_gain()
1719 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG); in b43_calc_loopback_gain()
1720 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER); in b43_calc_loopback_gain()
1721 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_calc_loopback_gain()
1723 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER); in b43_calc_loopback_gain()
1724 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); in b43_calc_loopback_gain()
1726 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A)); in b43_calc_loopback_gain()
1727 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59)); in b43_calc_loopback_gain()
1728 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58)); in b43_calc_loopback_gain()
1729 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A)); in b43_calc_loopback_gain()
1730 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03)); in b43_calc_loopback_gain()
1731 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK); in b43_calc_loopback_gain()
1732 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL); in b43_calc_loopback_gain()
1733 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B)); in b43_calc_loopback_gain()
1734 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL); in b43_calc_loopback_gain()
1735 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_calc_loopback_gain()
1737 backup_radio[0] = b43_radio_read16(dev, 0x52); in b43_calc_loopback_gain()
1738 backup_radio[1] = b43_radio_read16(dev, 0x43); in b43_calc_loopback_gain()
1739 backup_radio[2] = b43_radio_read16(dev, 0x7A); in b43_calc_loopback_gain()
1741 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF); in b43_calc_loopback_gain()
1742 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000); in b43_calc_loopback_gain()
1743 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002); in b43_calc_loopback_gain()
1744 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD); in b43_calc_loopback_gain()
1745 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001); in b43_calc_loopback_gain()
1746 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE); in b43_calc_loopback_gain()
1748 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001); in b43_calc_loopback_gain()
1749 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE); in b43_calc_loopback_gain()
1750 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002); in b43_calc_loopback_gain()
1751 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD); in b43_calc_loopback_gain()
1753 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); in b43_calc_loopback_gain()
1754 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); in b43_calc_loopback_gain()
1755 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030); in b43_calc_loopback_gain()
1756 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10); in b43_calc_loopback_gain()
1758 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); in b43_calc_loopback_gain()
1759 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_calc_loopback_gain()
1760 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_calc_loopback_gain()
1762 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); in b43_calc_loopback_gain()
1764 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); in b43_calc_loopback_gain()
1765 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB); in b43_calc_loopback_gain()
1767 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40); in b43_calc_loopback_gain()
1770 b43_radio_write16(dev, 0x43, 0x000F); in b43_calc_loopback_gain()
1772 b43_radio_write16(dev, 0x52, 0); in b43_calc_loopback_gain()
1773 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9); in b43_calc_loopback_gain()
1775 b43_gphy_set_baseband_attenuation(dev, 11); in b43_calc_loopback_gain()
1778 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); in b43_calc_loopback_gain()
1780 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); in b43_calc_loopback_gain()
1781 b43_phy_write(dev, B43_PHY_LO_CTL, 0); in b43_calc_loopback_gain()
1783 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01); in b43_calc_loopback_gain()
1784 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800); in b43_calc_loopback_gain()
1786 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); in b43_calc_loopback_gain()
1787 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); in b43_calc_loopback_gain()
1789 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) { in b43_calc_loopback_gain()
1791 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800); in b43_calc_loopback_gain()
1792 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000); in b43_calc_loopback_gain()
1795 b43_radio_mask(dev, 0x7A, 0x00F7); in b43_calc_loopback_gain()
1801 b43_radio_write16(dev, 0x43, i); in b43_calc_loopback_gain()
1802 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); in b43_calc_loopback_gain()
1803 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); in b43_calc_loopback_gain()
1804 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); in b43_calc_loopback_gain()
1806 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) in b43_calc_loopback_gain()
1814 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30); in b43_calc_loopback_gain()
1817 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); in b43_calc_loopback_gain()
1818 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); in b43_calc_loopback_gain()
1819 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); in b43_calc_loopback_gain()
1822 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) in b43_calc_loopback_gain()
1830 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]); in b43_calc_loopback_gain()
1831 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]); in b43_calc_loopback_gain()
1833 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]); in b43_calc_loopback_gain()
1834 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]); in b43_calc_loopback_gain()
1835 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]); in b43_calc_loopback_gain()
1836 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]); in b43_calc_loopback_gain()
1837 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]); in b43_calc_loopback_gain()
1838 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]); in b43_calc_loopback_gain()
1839 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]); in b43_calc_loopback_gain()
1840 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]); in b43_calc_loopback_gain()
1841 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]); in b43_calc_loopback_gain()
1843 b43_gphy_set_baseband_attenuation(dev, backup_bband); in b43_calc_loopback_gain()
1845 b43_radio_write16(dev, 0x52, backup_radio[0]); in b43_calc_loopback_gain()
1846 b43_radio_write16(dev, 0x43, backup_radio[1]); in b43_calc_loopback_gain()
1847 b43_radio_write16(dev, 0x7A, backup_radio[2]); in b43_calc_loopback_gain()
1849 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003); in b43_calc_loopback_gain()
1851 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]); in b43_calc_loopback_gain()
1852 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]); in b43_calc_loopback_gain()
1853 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]); in b43_calc_loopback_gain()
1854 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]); in b43_calc_loopback_gain()
1861 static void b43_hardware_pctl_early_init(struct b43_wldev *dev) in b43_hardware_pctl_early_init() argument
1863 struct b43_phy *phy = &dev->phy; in b43_hardware_pctl_early_init()
1865 if (!b43_has_hardware_pctl(dev)) { in b43_hardware_pctl_early_init()
1866 b43_phy_write(dev, 0x047A, 0xC111); in b43_hardware_pctl_early_init()
1870 b43_phy_mask(dev, 0x0036, 0xFEFF); in b43_hardware_pctl_early_init()
1871 b43_phy_write(dev, 0x002F, 0x0202); in b43_hardware_pctl_early_init()
1872 b43_phy_set(dev, 0x047C, 0x0002); in b43_hardware_pctl_early_init()
1873 b43_phy_set(dev, 0x047A, 0xF000); in b43_hardware_pctl_early_init()
1875 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); in b43_hardware_pctl_early_init()
1876 b43_phy_set(dev, 0x005D, 0x8000); in b43_hardware_pctl_early_init()
1877 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); in b43_hardware_pctl_early_init()
1878 b43_phy_write(dev, 0x002E, 0xC07F); in b43_hardware_pctl_early_init()
1879 b43_phy_set(dev, 0x0036, 0x0400); in b43_hardware_pctl_early_init()
1881 b43_phy_set(dev, 0x0036, 0x0200); in b43_hardware_pctl_early_init()
1882 b43_phy_set(dev, 0x0036, 0x0400); in b43_hardware_pctl_early_init()
1883 b43_phy_mask(dev, 0x005D, 0x7FFF); in b43_hardware_pctl_early_init()
1884 b43_phy_mask(dev, 0x004F, 0xFFFE); in b43_hardware_pctl_early_init()
1885 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); in b43_hardware_pctl_early_init()
1886 b43_phy_write(dev, 0x002E, 0xC07F); in b43_hardware_pctl_early_init()
1887 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); in b43_hardware_pctl_early_init()
1892 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev) in b43_hardware_pctl_init_gphy() argument
1894 struct b43_phy *phy = &dev->phy; in b43_hardware_pctl_init_gphy()
1897 if (!b43_has_hardware_pctl(dev)) { in b43_hardware_pctl_init_gphy()
1899 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL); in b43_hardware_pctl_init_gphy()
1903 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); in b43_hardware_pctl_init_gphy()
1904 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); in b43_hardware_pctl_init_gphy()
1905 b43_gphy_tssi_power_lt_init(dev); in b43_hardware_pctl_init_gphy()
1906 b43_gphy_gain_lt_init(dev); in b43_hardware_pctl_init_gphy()
1907 b43_phy_mask(dev, 0x0060, 0xFFBF); in b43_hardware_pctl_init_gphy()
1908 b43_phy_write(dev, 0x0014, 0x0000); in b43_hardware_pctl_init_gphy()
1911 b43_phy_set(dev, 0x0478, 0x0800); in b43_hardware_pctl_init_gphy()
1912 b43_phy_mask(dev, 0x0478, 0xFEFF); in b43_hardware_pctl_init_gphy()
1913 b43_phy_mask(dev, 0x0801, 0xFFBF); in b43_hardware_pctl_init_gphy()
1915 b43_gphy_dc_lt_init(dev, 1); in b43_hardware_pctl_init_gphy()
1918 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL); in b43_hardware_pctl_init_gphy()
1922 static void b43_phy_init_pctl(struct b43_wldev *dev) in b43_phy_init_pctl() argument
1924 struct b43_phy *phy = &dev->phy; in b43_phy_init_pctl()
1932 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && in b43_phy_init_pctl()
1933 (dev->dev->board_type == SSB_BOARD_BU4306)) in b43_phy_init_pctl()
1936 b43_phy_write(dev, 0x0028, 0x8018); in b43_phy_init_pctl()
1939 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0) in b43_phy_init_pctl()
1944 b43_hardware_pctl_early_init(dev); in b43_phy_init_pctl()
1947 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084); in b43_phy_init_pctl()
1964 b43_set_txpower_g(dev, &bbatt, &rfatt, 0); in b43_phy_init_pctl()
1966 b43_dummy_transmission(dev, false, true); in b43_phy_init_pctl()
1967 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI); in b43_phy_init_pctl()
1971 b43dbg(dev->wl, in b43_phy_init_pctl()
1980 b43_radio_mask(dev, 0x0076, 0xFF7B); in b43_phy_init_pctl()
1982 b43_set_txpower_g(dev, &old_bbatt, in b43_phy_init_pctl()
1986 b43_hardware_pctl_init_gphy(dev); in b43_phy_init_pctl()
1987 b43_shm_clear_tssi(dev); in b43_phy_init_pctl()
1990 static void b43_phy_initg(struct b43_wldev *dev) in b43_phy_initg() argument
1992 struct b43_phy *phy = &dev->phy; in b43_phy_initg()
1997 b43_phy_initb5(dev); in b43_phy_initg()
1999 b43_phy_initb6(dev); in b43_phy_initg()
2002 b43_phy_inita(dev); in b43_phy_initg()
2005 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0); in b43_phy_initg()
2006 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0); in b43_phy_initg()
2009 b43_phy_write(dev, B43_PHY_RFOVER, 0); in b43_phy_initg()
2010 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); in b43_phy_initg()
2013 b43_phy_write(dev, B43_PHY_RFOVER, 0x400); in b43_phy_initg()
2014 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); in b43_phy_initg()
2017 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM); in b43_phy_initg()
2020 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816); in b43_phy_initg()
2021 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); in b43_phy_initg()
2024 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00); in b43_phy_initg()
2028 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78); in b43_phy_initg()
2030 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80); in b43_phy_initg()
2031 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4); in b43_phy_initg()
2034 b43_calc_loopback_gain(dev); in b43_phy_initg()
2038 gphy->initval = b43_radio_init2050(dev); in b43_phy_initg()
2040 b43_radio_write16(dev, 0x0078, gphy->initval); in b43_phy_initg()
2042 b43_lo_g_init(dev); in b43_phy_initg()
2044 b43_radio_write16(dev, 0x52, in b43_phy_initg()
2045 (b43_radio_read16(dev, 0x52) & 0xFF00) in b43_phy_initg()
2049 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias); in b43_phy_initg()
2052 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); in b43_phy_initg()
2054 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_phy_initg()
2055 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); in b43_phy_initg()
2057 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); in b43_phy_initg()
2059 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101); in b43_phy_initg()
2061 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202); in b43_phy_initg()
2063 b43_lo_g_adjust(dev); in b43_phy_initg()
2064 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); in b43_phy_initg()
2067 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { in b43_phy_initg()
2074 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME? in b43_phy_initg()
2075 b43_calc_nrssi_threshold(dev); in b43_phy_initg()
2079 b43_calc_nrssi_slope(dev); in b43_phy_initg()
2081 b43_calc_nrssi_threshold(dev); in b43_phy_initg()
2084 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230); in b43_phy_initg()
2085 b43_phy_init_pctl(dev); in b43_phy_initg()
2089 if ((dev->dev->chip_id == 0x4306 in b43_phy_initg()
2090 && dev->dev->chip_pkg == 2) || 0) { in b43_phy_initg()
2091 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF); in b43_phy_initg()
2092 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); in b43_phy_initg()
2096 void b43_gphy_channel_switch(struct b43_wldev *dev, in b43_gphy_channel_switch() argument
2101 b43_synth_pu_workaround(dev, channel); in b43_gphy_channel_switch()
2103 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); in b43_gphy_channel_switch()
2106 if (dev->dev->bus_sprom->country_code == in b43_gphy_channel_switch()
2108 b43_hf_write(dev, in b43_gphy_channel_switch()
2109 b43_hf_read(dev) & ~B43_HF_ACPR); in b43_gphy_channel_switch()
2111 b43_hf_write(dev, in b43_gphy_channel_switch()
2112 b43_hf_read(dev) | B43_HF_ACPR); in b43_gphy_channel_switch()
2113 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_gphy_channel_switch()
2114 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_gphy_channel_switch()
2117 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_gphy_channel_switch()
2118 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_gphy_channel_switch()
2123 static void default_baseband_attenuation(struct b43_wldev *dev, in default_baseband_attenuation() argument
2126 struct b43_phy *phy = &dev->phy; in default_baseband_attenuation()
2134 static void default_radio_attenuation(struct b43_wldev *dev, in default_radio_attenuation() argument
2137 struct b43_bus_dev *bdev = dev->dev; in default_radio_attenuation()
2138 struct b43_phy *phy = &dev->phy; in default_radio_attenuation()
2142 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM && in default_radio_attenuation()
2143 dev->dev->board_type == SSB_BOARD_BCM4309G) { in default_radio_attenuation()
2144 if (dev->dev->board_rev < 0x43) { in default_radio_attenuation()
2147 } else if (dev->dev->board_rev < 0x51) { in default_radio_attenuation()
2235 static u16 default_tx_control(struct b43_wldev *dev) in default_tx_control() argument
2237 struct b43_phy *phy = &dev->phy; in default_tx_control()
2250 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel) in b43_gphy_aci_detect() argument
2252 struct b43_phy *phy = &dev->phy; in b43_gphy_aci_detect()
2258 saved = b43_phy_read(dev, 0x0403); in b43_gphy_aci_detect()
2259 b43_switch_channel(dev, channel); in b43_gphy_aci_detect()
2260 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5); in b43_gphy_aci_detect()
2262 rssi = b43_phy_read(dev, 0x048A) & 0x3F; in b43_gphy_aci_detect()
2269 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F; in b43_gphy_aci_detect()
2277 b43_phy_write(dev, 0x0403, saved); in b43_gphy_aci_detect()
2282 static u8 b43_gphy_aci_scan(struct b43_wldev *dev) in b43_gphy_aci_scan() argument
2284 struct b43_phy *phy = &dev->phy; in b43_gphy_aci_scan()
2292 b43_phy_lock(dev); in b43_gphy_aci_scan()
2293 b43_radio_lock(dev); in b43_gphy_aci_scan()
2294 b43_phy_mask(dev, 0x0802, 0xFFFC); in b43_gphy_aci_scan()
2295 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); in b43_gphy_aci_scan()
2296 b43_set_all_gains(dev, 3, 8, 1); in b43_gphy_aci_scan()
2303 ret[i - 1] = b43_gphy_aci_detect(dev, i); in b43_gphy_aci_scan()
2305 b43_switch_channel(dev, channel); in b43_gphy_aci_scan()
2306 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003); in b43_gphy_aci_scan()
2307 b43_phy_mask(dev, 0x0403, 0xFFF8); in b43_gphy_aci_scan()
2308 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); in b43_gphy_aci_scan()
2309 b43_set_original_gains(dev); in b43_gphy_aci_scan()
2317 b43_radio_unlock(dev); in b43_gphy_aci_scan()
2318 b43_phy_unlock(dev); in b43_gphy_aci_scan()
2352 u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev, in b43_generate_dyn_tssi2dbm_tab() argument
2361 b43err(dev->wl, "Could not allocate memory " in b43_generate_dyn_tssi2dbm_tab()
2368 b43err(dev->wl, "Could not generate " in b43_generate_dyn_tssi2dbm_tab()
2379 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev) in b43_gphy_init_tssi2dbm_table() argument
2381 struct b43_phy *phy = &dev->phy; in b43_gphy_init_tssi2dbm_table()
2385 pab0 = (s16) (dev->dev->bus_sprom->pa0b0); in b43_gphy_init_tssi2dbm_table()
2386 pab1 = (s16) (dev->dev->bus_sprom->pa0b1); in b43_gphy_init_tssi2dbm_table()
2387 pab2 = (s16) (dev->dev->bus_sprom->pa0b2); in b43_gphy_init_tssi2dbm_table()
2389 B43_WARN_ON((dev->dev->chip_id == 0x4301) && in b43_gphy_init_tssi2dbm_table()
2397 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 && in b43_gphy_init_tssi2dbm_table()
2398 (s8) dev->dev->bus_sprom->itssi_bg != -1) { in b43_gphy_init_tssi2dbm_table()
2400 (s8) (dev->dev->bus_sprom->itssi_bg); in b43_gphy_init_tssi2dbm_table()
2403 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, in b43_gphy_init_tssi2dbm_table()
2417 static int b43_gphy_op_allocate(struct b43_wldev *dev) in b43_gphy_op_allocate() argument
2428 dev->phy.g = gphy; in b43_gphy_op_allocate()
2437 err = b43_gphy_init_tssi2dbm_table(dev); in b43_gphy_op_allocate()
2451 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev) in b43_gphy_op_prepare_structs() argument
2453 struct b43_phy *phy = &dev->phy; in b43_gphy_op_prepare_structs()
2498 static void b43_gphy_op_free(struct b43_wldev *dev) in b43_gphy_op_free() argument
2500 struct b43_phy *phy = &dev->phy; in b43_gphy_op_free()
2511 dev->phy.g = NULL; in b43_gphy_op_free()
2514 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev) in b43_gphy_op_prepare_hardware() argument
2516 struct b43_phy *phy = &dev->phy; in b43_gphy_op_prepare_hardware()
2522 default_baseband_attenuation(dev, &gphy->bbatt); in b43_gphy_op_prepare_hardware()
2523 default_radio_attenuation(dev, &gphy->rfatt); in b43_gphy_op_prepare_hardware()
2524 gphy->tx_control = (default_tx_control(dev) << 4); in b43_gphy_op_prepare_hardware()
2525 generate_rfatt_list(dev, &lo->rfatt_list); in b43_gphy_op_prepare_hardware()
2526 generate_bbatt_list(dev, &lo->bbatt_list); in b43_gphy_op_prepare_hardware()
2529 b43_read32(dev, B43_MMIO_MACCTL); in b43_gphy_op_prepare_hardware()
2535 b43_wireless_core_reset(dev, 0); in b43_gphy_op_prepare_hardware()
2536 b43_phy_initg(dev); in b43_gphy_op_prepare_hardware()
2538 b43_wireless_core_reset(dev, 1); in b43_gphy_op_prepare_hardware()
2544 static int b43_gphy_op_init(struct b43_wldev *dev) in b43_gphy_op_init() argument
2546 b43_phy_initg(dev); in b43_gphy_op_init()
2551 static void b43_gphy_op_exit(struct b43_wldev *dev) in b43_gphy_op_exit() argument
2553 b43_lo_g_cleanup(dev); in b43_gphy_op_exit()
2556 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg) in b43_gphy_op_read() argument
2558 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_gphy_op_read()
2559 return b43_read16(dev, B43_MMIO_PHY_DATA); in b43_gphy_op_read()
2562 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_gphy_op_write() argument
2564 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_gphy_op_write()
2565 b43_write16(dev, B43_MMIO_PHY_DATA, value); in b43_gphy_op_write()
2568 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_gphy_op_radio_read() argument
2575 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_gphy_op_radio_read()
2576 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_gphy_op_radio_read()
2579 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_gphy_op_radio_write() argument
2584 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_gphy_op_radio_write()
2585 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_gphy_op_radio_write()
2588 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev) in b43_gphy_op_supports_hwpctl() argument
2590 return (dev->phy.rev >= 6); in b43_gphy_op_supports_hwpctl()
2593 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev, in b43_gphy_op_software_rfkill() argument
2596 struct b43_phy *phy = &dev->phy; in b43_gphy_op_software_rfkill()
2607 b43_phy_write(dev, 0x0015, 0x8000); in b43_gphy_op_software_rfkill()
2608 b43_phy_write(dev, 0x0015, 0xCC00); in b43_gphy_op_software_rfkill()
2609 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000)); in b43_gphy_op_software_rfkill()
2612 b43_phy_write(dev, B43_PHY_RFOVER, in b43_gphy_op_software_rfkill()
2614 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_gphy_op_software_rfkill()
2619 b43_gphy_channel_switch(dev, 6, 1); in b43_gphy_op_software_rfkill()
2620 b43_gphy_channel_switch(dev, channel, 0); in b43_gphy_op_software_rfkill()
2625 rfover = b43_phy_read(dev, B43_PHY_RFOVER); in b43_gphy_op_software_rfkill()
2626 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_gphy_op_software_rfkill()
2630 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C); in b43_gphy_op_software_rfkill()
2631 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73); in b43_gphy_op_software_rfkill()
2635 static int b43_gphy_op_switch_channel(struct b43_wldev *dev, in b43_gphy_op_switch_channel() argument
2640 b43_gphy_channel_switch(dev, new_channel, 0); in b43_gphy_op_switch_channel()
2645 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev) in b43_gphy_op_get_default_chan() argument
2650 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) in b43_gphy_op_set_rx_antenna() argument
2652 struct b43_phy *phy = &dev->phy; in b43_gphy_op_set_rx_antenna()
2659 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); in b43_gphy_op_set_rx_antenna()
2661 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, in b43_gphy_op_set_rx_antenna()
2666 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); in b43_gphy_op_set_rx_antenna()
2671 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); in b43_gphy_op_set_rx_antenna()
2674 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT); in b43_gphy_op_set_rx_antenna()
2679 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp); in b43_gphy_op_set_rx_antenna()
2682 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV); in b43_gphy_op_set_rx_antenna()
2684 b43_phy_mask(dev, B43_PHY_ANTWRSETT, in b43_gphy_op_set_rx_antenna()
2689 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10); in b43_gphy_op_set_rx_antenna()
2690 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15); in b43_gphy_op_set_rx_antenna()
2693 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); in b43_gphy_op_set_rx_antenna()
2695 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); in b43_gphy_op_set_rx_antenna()
2698 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC); in b43_gphy_op_set_rx_antenna()
2700 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); in b43_gphy_op_set_rx_antenna()
2703 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev, in b43_gphy_op_interf_mitigation() argument
2706 struct b43_phy *phy = &dev->phy; in b43_gphy_op_interf_mitigation()
2735 b43_radio_interference_mitigation_disable(dev, currentmode); in b43_gphy_op_interf_mitigation()
2741 b43_radio_interference_mitigation_enable(dev, mode); in b43_gphy_op_interf_mitigation()
2750 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) in b43_gphy_estimate_power_out() argument
2752 struct b43_phy_g *gphy = dev->phy.g; in b43_gphy_estimate_power_out()
2763 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev, in b43_put_attenuation_into_ranges() argument
2768 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; in b43_put_attenuation_into_ranges()
2816 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev) in b43_gphy_op_adjust_txpower() argument
2818 struct b43_phy *phy = &dev->phy; in b43_gphy_op_adjust_txpower()
2823 b43_mac_suspend(dev); in b43_gphy_op_adjust_txpower()
2831 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); in b43_gphy_op_adjust_txpower()
2841 } else if (dev->dev->bus_sprom-> in b43_gphy_op_adjust_txpower()
2860 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); in b43_gphy_op_adjust_txpower()
2864 if (b43_debug(dev, B43_DBG_XMITPOWER)) in b43_gphy_op_adjust_txpower()
2865 b43dbg(dev->wl, "Adjusting TX power\n"); in b43_gphy_op_adjust_txpower()
2868 b43_phy_lock(dev); in b43_gphy_op_adjust_txpower()
2869 b43_radio_lock(dev); in b43_gphy_op_adjust_txpower()
2870 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, in b43_gphy_op_adjust_txpower()
2872 b43_radio_unlock(dev); in b43_gphy_op_adjust_txpower()
2873 b43_phy_unlock(dev); in b43_gphy_op_adjust_txpower()
2875 b43_mac_enable(dev); in b43_gphy_op_adjust_txpower()
2878 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev, in b43_gphy_op_recalc_txpower() argument
2881 struct b43_phy *phy = &dev->phy; in b43_gphy_op_recalc_txpower()
2890 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK); in b43_gphy_op_recalc_txpower()
2891 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G); in b43_gphy_op_recalc_txpower()
2912 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi); in b43_gphy_op_recalc_txpower()
2915 max_pwr = dev->dev->bus_sprom->maxpwr_bg; in b43_gphy_op_recalc_txpower()
2916 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_gphy_op_recalc_txpower()
2919 b43warn(dev->wl, in b43_gphy_op_recalc_txpower()
2922 dev->dev->bus_sprom->maxpwr_bg = max_pwr; in b43_gphy_op_recalc_txpower()
2932 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_gphy_op_recalc_txpower()
2933 b43dbg(dev->wl, in b43_gphy_op_recalc_txpower()
2961 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_gphy_op_recalc_txpower()
2963 b43dbg(dev->wl, in b43_gphy_op_recalc_txpower()
2986 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev) in b43_gphy_op_pwork_15sec() argument
2988 struct b43_phy *phy = &dev->phy; in b43_gphy_op_pwork_15sec()
2991 b43_mac_suspend(dev); in b43_gphy_op_pwork_15sec()
2996 phy->ops->interf_mitigation(dev, in b43_gphy_op_pwork_15sec()
3000 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev)) in b43_gphy_op_pwork_15sec()
3001 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); in b43_gphy_op_pwork_15sec()
3007 b43_lo_g_maintenance_work(dev); in b43_gphy_op_pwork_15sec()
3008 b43_mac_enable(dev); in b43_gphy_op_pwork_15sec()
3011 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev) in b43_gphy_op_pwork_60sec() argument
3013 struct b43_phy *phy = &dev->phy; in b43_gphy_op_pwork_60sec()
3015 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) in b43_gphy_op_pwork_60sec()
3018 b43_mac_suspend(dev); in b43_gphy_op_pwork_60sec()
3019 b43_calc_nrssi_slope(dev); in b43_gphy_op_pwork_60sec()
3025 b43_switch_channel(dev, 1); in b43_gphy_op_pwork_60sec()
3027 b43_switch_channel(dev, 13); in b43_gphy_op_pwork_60sec()
3028 b43_switch_channel(dev, old_chan); in b43_gphy_op_pwork_60sec()
3030 b43_mac_enable(dev); in b43_gphy_op_pwork_60sec()