65 static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
67 	struct b43_phy *phy = &dev->phy;
82 static void b43_radio_set_tx_iq(struct b43_wldev *dev)  in b43_radio_set_tx_iq()  argument
86 	u16 tmp = b43_radio_read16(dev, 0x001E);  in b43_radio_set_tx_iq()
92 				b43_phy_write(dev, 0x0069,  in b43_radio_set_tx_iq()
100 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)  in aphy_channel_switch()  argument
106 	r8 = b43_radio_read16(dev, 0x0008);  in aphy_channel_switch()
107 	b43_write16(dev, 0x03F0, freq);  in aphy_channel_switch()
108 	b43_radio_write16(dev, 0x0008, r8);  in aphy_channel_switch()
111 	tmp = b43_radio_read16(dev, 0x002E);  in aphy_channel_switch()
114 	b43_radio_write16(dev, 0x002E, tmp);  in aphy_channel_switch()
123 	b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);  in aphy_channel_switch()
124 	b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);  in aphy_channel_switch()
125 	b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);  in aphy_channel_switch()
126 	b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4));  in aphy_channel_switch()
127 	b43_radio_write16(dev, 0x002A, (r8 << 4));  in aphy_channel_switch()
128 	b43_radio_write16(dev, 0x002B, (r8 << 4));  in aphy_channel_switch()
129 	b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4));  in aphy_channel_switch()
130 	b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0);  in aphy_channel_switch()
131 	b43_radio_write16(dev, 0x0035, 0x00AA);  in aphy_channel_switch()
132 	b43_radio_write16(dev, 0x0036, 0x0085);  in aphy_channel_switch()
133 	b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq));  in aphy_channel_switch()
134 	b43_radio_mask(dev, 0x003D, 0x00FF);  in aphy_channel_switch()
135 	b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080);  in aphy_channel_switch()
136 	b43_radio_mask(dev, 0x0035, 0xFFEF);  in aphy_channel_switch()
137 	b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010);  in aphy_channel_switch()
138 	b43_radio_set_tx_iq(dev);  in aphy_channel_switch()
143 static void b43_radio_init2060(struct b43_wldev *dev)  in b43_radio_init2060()  argument
145 	b43_radio_write16(dev, 0x0004, 0x00C0);  in b43_radio_init2060()
146 	b43_radio_write16(dev, 0x0005, 0x0008);  in b43_radio_init2060()
147 	b43_radio_write16(dev, 0x0009, 0x0040);  in b43_radio_init2060()
148 	b43_radio_write16(dev, 0x0005, 0x00AA);  in b43_radio_init2060()
149 	b43_radio_write16(dev, 0x0032, 0x008F);  in b43_radio_init2060()
150 	b43_radio_write16(dev, 0x0006, 0x008F);  in b43_radio_init2060()
151 	b43_radio_write16(dev, 0x0034, 0x008F);  in b43_radio_init2060()
152 	b43_radio_write16(dev, 0x002C, 0x0007);  in b43_radio_init2060()
153 	b43_radio_write16(dev, 0x0082, 0x0080);  in b43_radio_init2060()
154 	b43_radio_write16(dev, 0x0080, 0x0000);  in b43_radio_init2060()
155 	b43_radio_write16(dev, 0x003F, 0x00DA);  in b43_radio_init2060()
156 	b43_radio_mask(dev, 0x0005, ~0x0008);  in b43_radio_init2060()
157 	b43_radio_mask(dev, 0x0081, ~0x0010);  in b43_radio_init2060()
158 	b43_radio_mask(dev, 0x0081, ~0x0020);  in b43_radio_init2060()
159 	b43_radio_mask(dev, 0x0081, ~0x0020);  in b43_radio_init2060()
162 	b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010);  in b43_radio_init2060()
165 	b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008);  in b43_radio_init2060()
166 	b43_radio_mask(dev, 0x0085, ~0x0010);  in b43_radio_init2060()
167 	b43_radio_mask(dev, 0x0005, ~0x0008);  in b43_radio_init2060()
168 	b43_radio_mask(dev, 0x0081, ~0x0040);  in b43_radio_init2060()
169 	b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040);  in b43_radio_init2060()
170 	b43_radio_write16(dev, 0x0005,  in b43_radio_init2060()
171 			  (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);  in b43_radio_init2060()
172 	b43_phy_write(dev, 0x0063, 0xDDC6);  in b43_radio_init2060()
173 	b43_phy_write(dev, 0x0069, 0x07BE);  in b43_radio_init2060()
174 	b43_phy_write(dev, 0x006A, 0x0000);  in b43_radio_init2060()
176 	aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));  in b43_radio_init2060()
181 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)  in b43_phy_rssiagc()  argument
185 	if (dev->phy.rev < 3) {  in b43_phy_rssiagc()
188 				b43_ofdmtab_write16(dev,  in b43_phy_rssiagc()
190 				b43_ofdmtab_write16(dev,  in b43_phy_rssiagc()
195 				b43_ofdmtab_write16(dev,  in b43_phy_rssiagc()
197 				b43_ofdmtab_write16(dev,  in b43_phy_rssiagc()
203 				b43_ofdmtab_write16(dev,  in b43_phy_rssiagc()
207 				b43_ofdmtab_write16(dev,  in b43_phy_rssiagc()
212 static void b43_phy_ww(struct b43_wldev *dev)  in b43_phy_ww()  argument
217 	b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);  in b43_phy_ww()
218 	b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);  in b43_phy_ww()
219 	b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);  in b43_phy_ww()
220 	b43_radio_set(dev, 0x0009, 0x0080);  in b43_phy_ww()
221 	b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002);  in b43_phy_ww()
222 	b43_wa_initgains(dev);  in b43_phy_ww()
223 	b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);  in b43_phy_ww()
224 	b = b43_phy_read(dev, B43_PHY_PWRDOWN);  in b43_phy_ww()
225 	b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);  in b43_phy_ww()
226 	b43_radio_set(dev, 0x0004, 0x0004);  in b43_phy_ww()
228 		b43_radio_write16(dev, 0x0013, i);  in b43_phy_ww()
229 		curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;  in b43_phy_ww()
238 	b43_phy_write(dev, B43_PHY_PWRDOWN, b);  in b43_phy_ww()
239 	b43_radio_mask(dev, 0x0004, 0xFFFB);  in b43_phy_ww()
240 	b43_radio_write16(dev, 0x0013, best_s);  in b43_phy_ww()
241 	b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);  in b43_phy_ww()
242 	b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);  in b43_phy_ww()
243 	b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);  in b43_phy_ww()
244 	b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);  in b43_phy_ww()
245 	b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);  in b43_phy_ww()
246 	b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);  in b43_phy_ww()
247 	b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);  in b43_phy_ww()
248 	b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);  in b43_phy_ww()
249 	b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);  in b43_phy_ww()
250 	b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);  in b43_phy_ww()
251 	b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);  in b43_phy_ww()
253 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);  in b43_phy_ww()
254 	b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);  in b43_phy_ww()
255 	b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);  in b43_phy_ww()
256 	b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);  in b43_phy_ww()
257 	b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);  in b43_phy_ww()
258 	b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);  in b43_phy_ww()
261 static void hardware_pctl_init_aphy(struct b43_wldev *dev)  in hardware_pctl_init_aphy()  argument
266 void b43_phy_inita(struct b43_wldev *dev)  in b43_phy_inita()  argument
268 	struct b43_phy *phy = &dev->phy;  in b43_phy_inita()
280 			b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);  in b43_phy_inita()
281 		if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)  in b43_phy_inita()
282 			b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);  in b43_phy_inita()
284 			b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);  in b43_phy_inita()
287 	b43_wa_all(dev);  in b43_phy_inita()
291 			b43_phy_set(dev, 0x0034, 0x0001);  in b43_phy_inita()
292 		b43_phy_rssiagc(dev, 0);  in b43_phy_inita()
294 		b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);  in b43_phy_inita()
296 		b43_radio_init2060(dev);  in b43_phy_inita()
298 		if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&  in b43_phy_inita()
299 		    ((dev->dev->board_type == SSB_BOARD_BU4306) ||  in b43_phy_inita()
300 		     (dev->dev->board_type == SSB_BOARD_BU4309))) {  in b43_phy_inita()
305 			b43_phy_ww(dev);  in b43_phy_inita()
307 		hardware_pctl_init_aphy(dev);  in b43_phy_inita()
313 	    (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)) {  in b43_phy_inita()
314 		b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);  in b43_phy_inita()
319 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)  in b43_aphy_init_tssi2dbm_table()  argument
321 	struct b43_phy *phy = &dev->phy;  in b43_aphy_init_tssi2dbm_table()
325 	pab0 = (s16) (dev->dev->bus_sprom->pa1b0);  in b43_aphy_init_tssi2dbm_table()
326 	pab1 = (s16) (dev->dev->bus_sprom->pa1b1);  in b43_aphy_init_tssi2dbm_table()
327 	pab2 = (s16) (dev->dev->bus_sprom->pa1b2);  in b43_aphy_init_tssi2dbm_table()
332 		if ((s8) dev->dev->bus_sprom->itssi_a != 0 &&  in b43_aphy_init_tssi2dbm_table()
333 		    (s8) dev->dev->bus_sprom->itssi_a != -1)  in b43_aphy_init_tssi2dbm_table()
335 			    (s8) (dev->dev->bus_sprom->itssi_a);  in b43_aphy_init_tssi2dbm_table()
338 		aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,  in b43_aphy_init_tssi2dbm_table()
346 		b43err(dev->wl, "Could not generate tssi2dBm "  in b43_aphy_init_tssi2dbm_table()
354 static int b43_aphy_op_allocate(struct b43_wldev *dev)  in b43_aphy_op_allocate()  argument
362 	dev->phy.a = aphy;  in b43_aphy_op_allocate()
364 	err = b43_aphy_init_tssi2dbm_table(dev);  in b43_aphy_op_allocate()
372 	dev->phy.a = NULL;  in b43_aphy_op_allocate()
377 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)  in b43_aphy_op_prepare_structs()  argument
379 	struct b43_phy *phy = &dev->phy;  in b43_aphy_op_prepare_structs()
399 static void b43_aphy_op_free(struct b43_wldev *dev)  in b43_aphy_op_free()  argument
401 	struct b43_phy *phy = &dev->phy;  in b43_aphy_op_free()
408 	dev->phy.a = NULL;  in b43_aphy_op_free()
411 static int b43_aphy_op_init(struct b43_wldev *dev)  in b43_aphy_op_init()  argument
413 	b43_phy_inita(dev);  in b43_aphy_op_init()
418 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)  in adjust_phyreg()  argument
429 		b43err(dev->wl, "Invalid EXT-G PHY access at "  in adjust_phyreg()
435 		b43err(dev->wl, "Invalid N-BMODE PHY access at "  in adjust_phyreg()
444 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)  in b43_aphy_op_read()  argument
446 	reg = adjust_phyreg(dev, reg);  in b43_aphy_op_read()
447 	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);  in b43_aphy_op_read()
448 	return b43_read16(dev, B43_MMIO_PHY_DATA);  in b43_aphy_op_read()
451 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)  in b43_aphy_op_write()  argument
453 	reg = adjust_phyreg(dev, reg);  in b43_aphy_op_write()
454 	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);  in b43_aphy_op_write()
455 	b43_write16(dev, B43_MMIO_PHY_DATA, value);  in b43_aphy_op_write()
458 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)  in b43_aphy_op_radio_read()  argument
465 	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);  in b43_aphy_op_radio_read()
466 	return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);  in b43_aphy_op_radio_read()
469 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)  in b43_aphy_op_radio_write()  argument
474 	b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);  in b43_aphy_op_radio_write()
475 	b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);  in b43_aphy_op_radio_write()
478 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)  in b43_aphy_op_supports_hwpctl()  argument
480 	return (dev->phy.rev >= 5);  in b43_aphy_op_supports_hwpctl()
483 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,  in b43_aphy_op_software_rfkill()  argument
486 	struct b43_phy *phy = &dev->phy;  in b43_aphy_op_software_rfkill()
491 		b43_radio_write16(dev, 0x0004, 0x00C0);  in b43_aphy_op_software_rfkill()
492 		b43_radio_write16(dev, 0x0005, 0x0008);  in b43_aphy_op_software_rfkill()
493 		b43_phy_mask(dev, 0x0010, 0xFFF7);  in b43_aphy_op_software_rfkill()
494 		b43_phy_mask(dev, 0x0011, 0xFFF7);  in b43_aphy_op_software_rfkill()
495 		b43_radio_init2060(dev);  in b43_aphy_op_software_rfkill()
497 		b43_radio_write16(dev, 0x0004, 0x00FF);  in b43_aphy_op_software_rfkill()
498 		b43_radio_write16(dev, 0x0005, 0x00FB);  in b43_aphy_op_software_rfkill()
499 		b43_phy_set(dev, 0x0010, 0x0008);  in b43_aphy_op_software_rfkill()
500 		b43_phy_set(dev, 0x0011, 0x0008);  in b43_aphy_op_software_rfkill()
504 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,  in b43_aphy_op_switch_channel()  argument
509 	aphy_channel_switch(dev, new_channel);  in b43_aphy_op_switch_channel()
514 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)  in b43_aphy_op_get_default_chan()  argument
519 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)  in b43_aphy_op_set_rx_antenna()  argument
521 	struct b43_phy *phy = &dev->phy;  in b43_aphy_op_set_rx_antenna()
528 	b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);  in b43_aphy_op_set_rx_antenna()
530 	b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT,  in b43_aphy_op_set_rx_antenna()
535 		tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);  in b43_aphy_op_set_rx_antenna()
540 		b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);  in b43_aphy_op_set_rx_antenna()
543 		b43_phy_maskset(dev, B43_PHY_ANTDWELL, 0xFF00, 0x24);  in b43_aphy_op_set_rx_antenna()
545 		b43_phy_set(dev, B43_PHY_OFDM61, 0x10);  in b43_aphy_op_set_rx_antenna()
547 			b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x1D);  in b43_aphy_op_set_rx_antenna()
548 			b43_phy_write(dev, B43_PHY_ADIVRELATED, 8);  in b43_aphy_op_set_rx_antenna()
550 			b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x3A);  in b43_aphy_op_set_rx_antenna()
551 			b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8);  in b43_aphy_op_set_rx_antenna()
555 	b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);  in b43_aphy_op_set_rx_antenna()
558 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)  in b43_aphy_op_adjust_txpower()  argument
562 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,  in b43_aphy_op_recalc_txpower()  argument
568 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)  in b43_aphy_op_pwork_15sec()  argument
572 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)  in b43_aphy_op_pwork_60sec()  argument