Lines Matching refs:dma
130 _d->dma.status = TX_DMA_STATUS_DU; in wil_vring_alloc()
142 dma_addr_t pa = wil_desc_addr(&d->dma.addr); in wil_txdesc_unmap()
143 u16 dmalen = le16_to_cpu(d->dma.length); in wil_txdesc_unmap()
198 pa = wil_desc_addr(&d->dma.addr); in wil_vring_free()
199 dmalen = le16_to_cpu(d->dma.length); in wil_vring_free()
239 d->dma.d0 = RX_DMA_D0_CMD_DMA_RT | RX_DMA_D0_CMD_DMA_IT; in wil_vring_alloc_skb()
240 wil_desc_addr_set(&d->dma.addr, pa); in wil_vring_alloc_skb()
244 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */ in wil_vring_alloc_skb()
245 d->dma.length = cpu_to_le16(sz); in wil_vring_alloc_skb()
296 if (d->dma.status & RX_DMA_STATUS_PHY_INFO) { in wil_rx_add_radiotap_header()
334 if (d->dma.status & RX_DMA_STATUS_ERROR) in wil_rx_add_radiotap_header()
400 if (unlikely(!(_d->dma.status & RX_DMA_STATUS_DU))) { in wil_vring_reap_rx()
414 pa = wil_desc_addr(&d->dma.addr); in wil_vring_reap_rx()
417 dmalen = le16_to_cpu(d->dma.length); in wil_vring_reap_rx()
498 if (likely(d->dma.status & RX_DMA_STATUS_L4I)) { in wil_vring_reap_rx()
500 if (likely((d->dma.error & RX_DMA_ERROR_L4_ERR) == 0)) in wil_vring_reap_rx()
1081 wil_desc_addr_set(&d->dma.addr, pa); in wil_tx_desc_map()
1082 d->dma.ip_length = 0; in wil_tx_desc_map()
1084 d->dma.b11 = 0/*14 | BIT(7)*/; in wil_tx_desc_map()
1085 d->dma.error = 0; in wil_tx_desc_map()
1086 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */ in wil_tx_desc_map()
1087 d->dma.length = cpu_to_le16((u16)len); in wil_tx_desc_map()
1088 d->dma.d0 = (vring_index << DMA_CFG_DESC_TX_0_QID_POS); in wil_tx_desc_map()
1118 d->dma.b11 = ETH_HLEN; /* MAC header length */ in wil_tx_desc_offload_setup_tso()
1119 d->dma.b11 |= is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; in wil_tx_desc_offload_setup_tso()
1121 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); in wil_tx_desc_offload_setup_tso()
1123 d->dma.d0 |= (tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); in wil_tx_desc_offload_setup_tso()
1126 d->dma.d0 |= (BIT(DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS)) | in wil_tx_desc_offload_setup_tso()
1128 d->dma.d0 |= (is_ipv4 << DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS); in wil_tx_desc_offload_setup_tso()
1130 d->dma.ip_length = skb_net_hdr_len; in wil_tx_desc_offload_setup_tso()
1132 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); in wil_tx_desc_offload_setup_tso()
1134 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); in wil_tx_desc_offload_setup_tso()
1154 d->dma.b11 = ETH_HLEN; /* MAC header length */ in wil_tx_desc_offload_setup()
1159 d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS); in wil_tx_desc_offload_setup()
1170 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); in wil_tx_desc_offload_setup()
1172 d->dma.d0 |= in wil_tx_desc_offload_setup()
1177 d->dma.d0 |= in wil_tx_desc_offload_setup()
1184 d->dma.ip_length = skb_network_header_len(skb); in wil_tx_desc_offload_setup()
1186 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); in wil_tx_desc_offload_setup()
1188 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); in wil_tx_desc_offload_setup()
1195 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS) | in wil_tx_last_desc()
1202 d->dma.d0 |= wil_tso_type_lst << in wil_set_tx_desc_last_tso()
1482 _desc->dma.status = TX_DMA_STATUS_DU; in __wil_tx_vring_tso()
1579 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS); in __wil_tx_vring()
1580 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS); in __wil_tx_vring()
1581 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); in __wil_tx_vring()
1626 _d->dma.status = TX_DMA_STATUS_DU; in __wil_tx_vring()
1782 if (unlikely(!(_d->dma.status & TX_DMA_STATUS_DU))) in wil_tx_complete()
1797 dmalen = le16_to_cpu(d->dma.length); in wil_tx_complete()
1799 d->dma.error); in wil_tx_complete()
1803 d->dma.status, d->dma.error); in wil_tx_complete()
1810 if (likely(d->dma.error == 0)) { in wil_tx_complete()
1822 wil_consume_skb(skb, d->dma.error == 0); in wil_tx_complete()