Lines Matching refs:wil
77 static void wil6210_mask_irq_tx(struct wil6210_priv *wil) in wil6210_mask_irq_tx() argument
79 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_tx()
83 static void wil6210_mask_irq_rx(struct wil6210_priv *wil) in wil6210_mask_irq_rx() argument
85 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_rx()
89 static void wil6210_mask_irq_misc(struct wil6210_priv *wil) in wil6210_mask_irq_misc() argument
91 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_misc()
95 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) in wil6210_mask_irq_pseudo() argument
97 wil_dbg_irq(wil, "%s()\n", __func__); in wil6210_mask_irq_pseudo()
99 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE); in wil6210_mask_irq_pseudo()
101 clear_bit(wil_status_irqen, wil->status); in wil6210_mask_irq_pseudo()
104 void wil6210_unmask_irq_tx(struct wil6210_priv *wil) in wil6210_unmask_irq_tx() argument
106 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_tx()
110 void wil6210_unmask_irq_rx(struct wil6210_priv *wil) in wil6210_unmask_irq_rx() argument
112 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_rx()
116 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil) in wil6210_unmask_irq_misc() argument
118 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_misc()
122 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) in wil6210_unmask_irq_pseudo() argument
124 wil_dbg_irq(wil, "%s()\n", __func__); in wil6210_unmask_irq_pseudo()
126 set_bit(wil_status_irqen, wil->status); in wil6210_unmask_irq_pseudo()
128 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK); in wil6210_unmask_irq_pseudo()
131 void wil_mask_irq(struct wil6210_priv *wil) in wil_mask_irq() argument
133 wil_dbg_irq(wil, "%s()\n", __func__); in wil_mask_irq()
135 wil6210_mask_irq_tx(wil); in wil_mask_irq()
136 wil6210_mask_irq_rx(wil); in wil_mask_irq()
137 wil6210_mask_irq_misc(wil); in wil_mask_irq()
138 wil6210_mask_irq_pseudo(wil); in wil_mask_irq()
141 void wil_unmask_irq(struct wil6210_priv *wil) in wil_unmask_irq() argument
143 wil_dbg_irq(wil, "%s()\n", __func__); in wil_unmask_irq()
145 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
147 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
149 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
152 wil6210_unmask_irq_pseudo(wil); in wil_unmask_irq()
153 wil6210_unmask_irq_tx(wil); in wil_unmask_irq()
154 wil6210_unmask_irq_rx(wil); in wil_unmask_irq()
155 wil6210_unmask_irq_misc(wil); in wil_unmask_irq()
158 void wil_configure_interrupt_moderation(struct wil6210_priv *wil) in wil_configure_interrupt_moderation() argument
160 wil_dbg_irq(wil, "%s()\n", __func__); in wil_configure_interrupt_moderation()
165 if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) in wil_configure_interrupt_moderation()
169 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
170 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
171 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
172 wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
174 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, in wil_configure_interrupt_moderation()
178 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
179 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
180 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
181 wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
183 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN | in wil_configure_interrupt_moderation()
187 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
188 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
189 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
190 wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
192 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, in wil_configure_interrupt_moderation()
196 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
197 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
198 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
199 wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
201 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN | in wil_configure_interrupt_moderation()
207 struct wil6210_priv *wil = cookie; in wil6210_irq_rx() local
208 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
214 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx()
217 wil_err(wil, "spurious IRQ: RX\n"); in wil6210_irq_rx()
221 wil6210_mask_irq_rx(wil); in wil6210_irq_rx()
231 wil_dbg_irq(wil, "RX done\n"); in wil6210_irq_rx()
234 wil_err_ratelimited(wil, in wil6210_irq_rx()
239 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx()
240 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx()
241 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); in wil6210_irq_rx()
243 napi_schedule(&wil->napi_rx); in wil6210_irq_rx()
245 wil_err(wil, in wil6210_irq_rx()
249 wil_err(wil, "Got Rx interrupt while in reset\n"); in wil6210_irq_rx()
254 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx()
258 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx()
261 wil6210_unmask_irq_rx(wil); in wil6210_irq_rx()
268 struct wil6210_priv *wil = cookie; in wil6210_irq_tx() local
269 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
275 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx()
278 wil_err(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx()
282 wil6210_mask_irq_tx(wil); in wil6210_irq_tx()
285 wil_dbg_irq(wil, "TX done\n"); in wil6210_irq_tx()
289 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx()
290 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx()
292 napi_schedule(&wil->napi_tx); in wil6210_irq_tx()
294 wil_err(wil, "Got Tx interrupt while in reset\n"); in wil6210_irq_tx()
299 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); in wil6210_irq_tx()
303 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx()
306 wil6210_unmask_irq_tx(wil); in wil6210_irq_tx()
311 static void wil_notify_fw_error(struct wil6210_priv *wil) in wil_notify_fw_error() argument
313 struct device *dev = &wil_to_ndev(wil)->dev; in wil_notify_fw_error()
319 wil_err(wil, "Notify about firmware error\n"); in wil_notify_fw_error()
323 static void wil_cache_mbox_regs(struct wil6210_priv *wil) in wil_cache_mbox_regs() argument
326 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
328 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); in wil_cache_mbox_regs()
329 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); in wil_cache_mbox_regs()
334 struct wil6210_priv *wil = cookie; in wil6210_irq_misc() local
335 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
340 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); in wil6210_irq_misc()
343 wil_err(wil, "spurious IRQ: MISC\n"); in wil6210_irq_misc()
347 wil6210_mask_irq_misc(wil); in wil6210_irq_misc()
350 u32 fw_assert_code = wil_r(wil, RGF_FW_ASSERT_CODE); in wil6210_irq_misc()
351 u32 ucode_assert_code = wil_r(wil, RGF_UCODE_ASSERT_CODE); in wil6210_irq_misc()
353 wil_err(wil, in wil6210_irq_misc()
356 clear_bit(wil_status_fwready, wil->status); in wil6210_irq_misc()
365 wil_dbg_irq(wil, "IRQ: FW ready\n"); in wil6210_irq_misc()
366 wil_cache_mbox_regs(wil); in wil6210_irq_misc()
367 set_bit(wil_status_mbox_ready, wil->status); in wil6210_irq_misc()
375 wil->isr_misc = isr; in wil6210_irq_misc()
380 wil6210_unmask_irq_misc(wil); in wil6210_irq_misc()
387 struct wil6210_priv *wil = cookie; in wil6210_irq_misc_thread() local
388 u32 isr = wil->isr_misc; in wil6210_irq_misc_thread()
391 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); in wil6210_irq_misc_thread()
394 wil_fw_core_dump(wil); in wil6210_irq_misc_thread()
395 wil_notify_fw_error(wil); in wil6210_irq_misc_thread()
397 wil_fw_error_recovery(wil); in wil6210_irq_misc_thread()
401 wil_dbg_irq(wil, "MBOX event\n"); in wil6210_irq_misc_thread()
402 wmi_recv_cmd(wil); in wil6210_irq_misc_thread()
407 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); in wil6210_irq_misc_thread()
409 wil->isr_misc = 0; in wil6210_irq_misc_thread()
411 wil6210_unmask_irq_misc(wil); in wil6210_irq_misc_thread()
421 struct wil6210_priv *wil = cookie; in wil6210_thread_irq() local
423 wil_dbg_irq(wil, "Thread IRQ\n"); in wil6210_thread_irq()
425 if (wil->isr_misc) in wil6210_thread_irq()
428 wil6210_unmask_irq_pseudo(wil); in wil6210_thread_irq()
439 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) in wil6210_debug_irq_mask() argument
441 if (!test_bit(wil_status_irqen, wil->status)) { in wil6210_debug_irq_mask()
442 u32 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
445 u32 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
448 u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR + in wil6210_debug_irq_mask()
450 u32 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
453 u32 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
456 u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR + in wil6210_debug_irq_mask()
458 u32 icm_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
461 u32 icr_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
464 u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR + in wil6210_debug_irq_mask()
466 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" in wil6210_debug_irq_mask()
484 struct wil6210_priv *wil = cookie; in wil6210_hardirq() local
485 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE); in wil6210_hardirq()
494 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause))) in wil6210_hardirq()
498 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); in wil6210_hardirq()
500 wil6210_mask_irq_pseudo(wil); in wil6210_hardirq()
529 wil6210_unmask_irq_pseudo(wil); in wil6210_hardirq()
542 void wil6210_clear_irq(struct wil6210_priv *wil) in wil6210_clear_irq() argument
544 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_clear_irq()
546 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_clear_irq()
548 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_clear_irq()
553 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi) in wil6210_init_irq() argument
557 wil_dbg_misc(wil, "%s(%s)\n", __func__, use_msi ? "MSI" : "INTx"); in wil6210_init_irq()
562 WIL_NAME, wil); in wil6210_init_irq()
566 void wil6210_fini_irq(struct wil6210_priv *wil, int irq) in wil6210_fini_irq() argument
568 wil_dbg_misc(wil, "%s()\n", __func__); in wil6210_fini_irq()
570 wil_mask_irq(wil); in wil6210_fini_irq()
571 free_irq(irq, wil); in wil6210_fini_irq()